When to use `include in SystemVerilog

Question

i was wondering what's the use of the `include preprocessor directive and when to use it. For example i was using Xilinx's Vivado and i tried this:

module A (          //This is the top module 
    input  logic x, y,
    output logic z
    );
    
    B B1 (.a(x),
          .b(y),
          .c(z)
          );
endmodule

I wrote in a different file this

module B(
    input  logic a, b,
    output logic c
        );
        
        assign c = a & b;
endmodule

The software didn't warn me of anything and it synthetized correctly. So now I'm a little bit confused, also I've seen people that include every file in their top module other people that include only their parmeters and packages.

Answer 1

In order for verilog to compile your model you need to provide all files which contain relevant code in one of two ways:

1. list of files at command line
2. use `include

Method #1 assumes a certain compilation order (first to last). However, it does not matter in which order design elements (modules, primitives, ...) are compiled. The compiler can always locate a module either compiled before or after the code which instantiates it.

Certain verilog elements require a specific order of compilation. In classic verilog those are macro definitions (`define). System verilog adds packages and definitions in global scope. If your files contain those elements, they must be listed before the code which uses them.

The other case, related mostly to pre-system verilog world, is to use `include to insert common parameter definitions in scopes of modules. This way the statement appears inside of the module. In system verilog this can be replaced with packages and import statements.

For order-dependent compilation elements you can put them in the compilation list before the code which uses them. However at times the order could be difficult to implement. `includes help in this situation. They alow you to guarantee the order of compilation and also group related files together.

Verilog allows you to `include any code, it just does not care. However, in my experience, `include of code which contains design elements (modules) can cause code management issues and can cause compilation issues in some cases.