Add delay in Ripple carry in VHDL

Question

I'm banging my head for three days in a row for this problem.. that is, I can't insert delays to the full adders of a 3-bit RCA. Unfortunately I tried to add them in the full-adders code but only one full adder respects the delay, while the other two don't. So I wanted to know if it was possible to add delays to the 3-bit RCA code specifically in the port map section.

Help me get out of it.

Thank you

Here is my code...

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity RCA_3 is
Port (
A : in STD_LOGIC_VECTOR (2 downto 0);
B : in STD_LOGIC_VECTOR (2 downto 0);
Cin : in STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 2 downto 0);
Cout : out STD_LOGIC);
end RCA_3;


architecture Behavioral of RCA_3 is

component full_adder
Port ( 
a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end component;

signal c1,c2: STD_LOGIC; 

begin

--here i have a trouble

process is
begin 

wait for 10 ns;
FA1: full_adder port map( a => A(0), b => B(0), cin => Cin, sum => S(0), cout => c1);
wait for 10 ns;
FA2: full_adder port map( a => A(1), b => B(1), cin => c1, sum => S(1), cout => c2);
wait for 10 ns;
FA3: full_adder port map( a => A(2), b => B(2), cin => c2, sum => S(2), cout => Cout);
wait for 10 ns;

end process;
end Behavioral;

Answer 1

I don't know your FullAdder code, but I think it is something like this:

entity full_adder is
    Port (
    a    : in  STD_LOGIC;
    b    : in  STD_LOGIC;
    cin  : in  STD_LOGIC;
    s    : out STD_LOGIC;
    cout : out STD_LOGIC);
end full_adder;

architecture bhv of full_adder is
begin
    s <= a XOR b XOR cin;
    cout <= (a AND b) OR (cin AND a) OR (cin AND b);
end bhv;

You can now just write something like this:

    s <= a XOR b XOR cin after 10 ns;
    cout <= (a AND b) OR (cin AND a) OR (cin AND b) after 10 ns;

You won't need any further delay when you instance the full adder.

FYI: You can use the for-generate-Statement to make a more generic implementation of your Full Adder.

And I recommend you to use STD_ULOGIC insteand of STD_LOGIC, because in most cases you don't want a signal to have multiple drivers. Especially when writing code for FPGAs or ASICs you have to avoid such signals until you don't know what you are doing or how to treat them.