Translating From Virtual to Physical Memory?

Question

In 32 bit OS translating from virtual to physical memory is done like this:

But in 64 bit it's done like this:

Isn't this really strange? Why the first layer in 32 bit is PDE but the first layer in 64 bit isn't? Plus in 64 bit why all are not PDE except the last one. (As PTE holds some flags which are related to physical memory so why to repeat same info 3 times)?

Answer 1

The intel documentation has the entries in 64-bit labeled like this:

PML4-Entry -> [anon., Pg. Dir. Ptr.] -> Pg. Dir-Entry ->
-> Page Tbl.-Entry -> phys. Address.

On the last two (table and directories) everyone can agree, but then it gets less clear in the upper levels.

So your second figure uses PTE in a unspecific way. PSE might be a more general term:

Formats of CR3 and Paging-Structure Entries with 4-Level Paging and 5-Level Paging

(caption of figure 4-11 in SDM vol. 3; contains also PDPTE , PML4E and PML5E as missing names)

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The only bit unique to PTE seems to be PAT. The other levels also have minor differences, except PML4 and PML5.

A PDPTE (level 3) can hold a PD-Address, but also a 1GB page; then the "physical" flags are needed (for PAT a different bit is used).

Same for PDE and direct 2MB page frames.

This gives three groups of paging structures:

PML5, PML4: for hierarchical access
PDPT, PD:   for hier. and (or) direct mapping
PT:         for mapping 

The physical layout is uniform, but the semantics change slightly from level to level. Even CR3 can hold either a PML4- or PML5-table address.