SystemVerilog dist constraint

Question

I'm missing something in how to setup a dist constraint. I'm trying to get an equal weight between two ranges [0:31] and [32:65535]. I've set up a simple test:

class data;
  rand bit [15:0] field1;
  constraint c_f1 { field1 dist {[0:31] := 1, [32:65535] := 1};}
endclass

module testbench;
   
  initial begin
    data test_h;
    test_h = new();
    
    repeat(10) begin
        assert(test_h.randomize());
        $display("field1 = %h", test_h.field1);
    end
  end

endmodule

However, I'm seeing most values > 32. What have I misunderstood here?

Answer 1

Use the :/ operator instead of the := operator. Change:

  constraint c_f1 { field1 dist {[0:31] := 1, [32:65535] := 1};}

to:

  constraint c_f1 { field1 dist {[0:31] :/ 1, [32:65535] :/ 1};}

Refer to IEEE Std 1800-2017, section 18.5.4 Distribution .

The:/ operator assigns the specified weight to the item or, if the item is a range, to the range as a whole. If there are n values in the range, the weight of each value is range_weight / n.

This gives more values between 0-31:

field1 = 0012
field1 = 001f
field1 = 000f
field1 = a138
field1 = 0018
field1 = 001c
field1 = 9d48
field1 = 0009
field1 = 85bf
field1 = f930