MPU subregions security for STM32H7

Question

I am trying to understand the STM32H7 MPU example , In this example, only one region has been created for all the memory address space 4GB.
The subregion option is activated which means, it will be divided into 8 subregions starting from 0x0.
And SRD is set to 0x87 which means the MPU will be enabled only on: On-chip peripheral address space, external RAM, Shared device space.
This seems strange to me because we kept the most important address space unprotected for Flash, SRAM, System, and Non-shareable devices.
Any explanation of the reason the subregions were configured that way?

Answer 1

When a ThreadX Module thread is scheduled, the MPU is reconfigured such that the module can only access its code and data memory.

Answer 2

One background region is created during initialization. This region is the only active one for privileged code. Module specific regions are configured every time there is a task switch into user code. More information here: https://developer.arm.com/documentation/dui0646/c/Cortex-M7-Peripherals/Optional-Memory-Protection-Unit?lang=en