Configuring 256 different priority levels for each interrupt in ARM Cortex-M4

Question

I am working with ARM Cortex-M4 interrupts. I had enabled the core to handle a maximum of 240 interrupts. I have also enabled the interrupts. But while trying to set the priority of the interrupts, I can see that its not working as expected. If I have 50 interrupts coming in, say, I want to set the priority of the 50th signal as 50, it's not working. From what I have seen ( https://i.stack.imgur.com/puqs1.png ), it looks like the priority field supports only 4 bits. so that will give me a very limited option of setting the priority up to 16. Is there a way to set the priority to a number equal to 256 since they have mentioned that we can have a maximum of 256 levels of interrupt priority. Am I missing something or have misunderstood the concept?!

CASE 1:

1. Enabled all 50 interrupts.
2. Set the interrupt priorities with the 1st Int having priority 1 and 50 having 50 using (NVIC_SetPriority((IRQn_Type) 1, 1)), NVIC_SetPriority((IRQn_Type) 50, 50) .
3. Activated all 50 interrupts at once. Expected behaviour: 1 getting serviced first and 50 getting serviced at the end. Actual behaviour: completely random servicing of interrupts. Priority not followed.

CASE 2:

1. Enabled few interrupts.
2. Set the priority to 16 interrupts (1-16) Working as expected, 1st interrupt getting serviced first and 16 getting serviced at the end.

Answer 1

ARM leaves it up to the silicon vendor how many levels of interrupt priority to implement, up to a maximum of 256. They usually don't implement the maximum because it increases cost, size and power consumption.

The silicon vendor tells the software engineer how many they chose in the CMSIS headers with the constant __NVIC_PRIO_BITS .

I have personally worked with parts where this has the value 2, 3 or 4. It sounds like your part has 4, for 16 priority levels.

16 Levels of interrupt priority is absolutely loads for almost any real world application. If you need more than this I suggest you go back to your system level design!

It isn't necessary to give every interrupt its own priority like you are attempting. You should keep your routines nice and short so the latency is acceptable to the ones who have to wait.

Also you should note that the order that interrupts are handled is always completely deterministic, never random as you complain. If you give two interrupts the same priority and they occur at the exact same time then the one with the lower interrupt number will always be serviced first.