How to calculate the miss rate of Data and Instruction Caches

Question

The Situation

I'm trying to answer an architecture question on instruction and data caches I have found in a past exam paper ( not homework! ).

The question seems to give a lot of information which I haven't used in my solution. This makes me think I'm missing something and would be really grateful if someone could help me out!

The (Full) Question

This is the full question as asked in the paper. For a summary of key points please see below.

Calculate the miss rate for a machine S with separate instruction cache and data cache, each of n bytes. There are I misses per K instructions for the instruction cache, and d misses per k instructions for the data cache.

A fraction X of instructions involve data transfer, while a fraction Y of instructions contain instruction references, the rest contain data references. A hit takes H cycles and the miss penalty is M cycles.

Key Question Points

Given :

• Data and instruction caches are separate
• Each cache has N bytes
• I misses per K instructions for instruction cache
• D misses per K instructions for the data cache
• A fraction X of the instructions involve data transfer
• A fraction Y of the instructions involve instruction references
• The rest of the instructions contain instruction references
• A hit takes H cycles
• The miss penalty is M cycles

Calculate : Miss Rate of Machine

Attempts so far

I originally thought that the miss rate would be (I/K)*Y + (D/K)*(1 - X - Y) but since this doesn't use all the data provided, I don't think it can be right :(.

Any help would be awesome!

Answer 1

I think that you maybe interpreting the question wrong or the question is not well framed. Miss rate of cache is obviously no. of misses/total no. of accesses no. of misses/total no. of accesses no. of misses/total no. of accesses . The only thing I can think of which uses all the info of the question is calculating the miss penalty for a cache miss

Answer 2

命中时间L1 + Miss rateL1 *（命中时间L2 + Miss rateL2 * Miss penatlyL2）