Automatic recompile on compiler flag change

Question

As I was debugging and optimizing one of my C/C++-projects, I often disabled and enables the profiling flags -p -g -pg and some optimization flags in my Makefile to have a better look at whats happening.

However, GNU make did not detect this change and did not do a recompile.

How to properly rebuild a whole software project with some new flags (or some removed) without manually doing a make clean ?

Answer 1

As a suggested tweak to Stefan's above response, you can factor out build configuration into a separate file. Instead of somehow force-including this file in your code, you can list the name of this configuration file as a prereq (ie to the right of the colon) for all makefile rules you use to build code.

Answer 2

The basic thing one has to do is making every object depend on a config file.

As a slightly insane solution for c/c++ one can use a file like below which is correct syntax for both makefiles and c/c++.

Instead of having all the compiler flags in the Makefile itself, I create the following file "Makefile_flags":

#undef DUMMY
#define DUMMY /*
PROFILING_FLAGS = -p -g -pg
OPTIMIZATION_FLAGS = -O3
COMPILE_FLAGS = -Wall -Wextra -Wuninitialized -Wmissing-declarations \
                -Wshadow -ftrapv -Wfloat-equal -Wundef -Wpointer-arith \
                -Wcast-align -Wunreachable-code -Wold-style-cast \
                -Wformat=2 -Winit-self -Werror-implicit-function-declaration \
                -Wredundant-decls -Wunsafe-loop-optimizations \
                -pedantic -MD -MP
CPP_STD_FLAGS = -std=c++0x
COMPILE_FLAGS += $(CPP_STD_FLAGS)
COMPILE_FLAGS += $(PROFILING_FLAGS)
COMPILE_FLAGS += $(OPTIMIZATION_FLAGS)
LINKING_FLAGS = $(COMPILE_FLAGS)
#foo */

Now write -include Makefile_flags in your Makefile and #include "Makefile_flags" in every file of your source code you want to have updated (eg in every *.c / *.cpp file).

The beauty of this solution: The Makefile uses # as symbol for comments, thus #undef DUMMY , #define DUMMY /* and #foo */ have no effect here. In C/C++ however, /* is used for multiline comments. Thus, the whole non-C-code is ignored by the compiler and the unknown symbol /* is not seen by the Makefile. Additionally, the pre-processor instruction #undef DUMMY takes care of not doing #define DUMMY twice and the #foo statement is inside of the multi-line-comment.

The downside however is, that one must include it in every file.

Make sure that you have the right relative path to your file "Makefile_flags".

Answer 3

The solution to exactly this problem is built into makepp . That automatically detects and takes into account all dependencies, and a changed command is of course one of them.

Answer 4

You could just use a smarter build system, if possible. I use SCons and it has stuff like this built it. It also has nice features like automatically scanning your files for header dependencies so you don't have to manually keep that up to date or run 20 autotools.