If Statement VHDL

Question

Can some one explain why the golden rule when writing VHDL is that the if-then-else statement must be in a process. Is it because inside the process, the statements are executed sequentially, while outside they're not.

Answer 1

The simple answer is "because that's how the syntax of the language is"!

If you want to select from some options with code not in a process you can do:

sig <= a when sel = 1 else
       b when sel = 2 else 
       default_value;

or

with sel select
   sig <= a when 1,
          b when 2,
          default_value when others;

See here for many examples of a mux

Answer 2

I might be wrong, but I think the main reason that if statements need to be in a process is that an if statement can potentially assign to more than one signal, if you wanted to do the same thing outside of a process you would need to use more than one conditional signal assignment.

For example:

process(C0, C1, A, B, C) is
begin
  if C0 = '1' then
    F <= A;
    G <= C;
  elsif C1 = '1' then
    F <= B;
    G <= B;
  else
    F <= C;
    G <= A;
  end if;
end process;

The equivalent conditional signal assignments outside of the process would be:

F <= A when C0 = '1' else B when C1 = '1' else C;
G <= C when C0 = '1' else B when C1 = '1' else A;

Answer 3

if else statement :-

Syntax:
if then
statements
...
[
elsif then
statements
...
else
statements
...
]
endif;

for more information please check this