MSP430 assembly instructions

Question

I am trying to understand what these instructions do for the MSP 430 processor:

(1) MOV.w  #0x0055,R5
(2)   BIC.w  #0xFFEE,R5
(3)   BIS.w  #0x1144,R5

I haven't been able to find much that explains the assembly instructions and would love to find out what these instructions do and what is stored in the r5 register after each instruction. Could someone explain?

Answer 1

MOV moves a value to the destination. In this case R5 will contain the value 0x0055.

BIC clears bits in the destination value. If R5 would contain 0x0055 before the instruction, it will contain the value 0x0011. (Think of this as an inversed and instruction).

BIS sets bits -- this is effectively the same as an or operation. R5 will have the value 0x1155 after this instruction.

Answer 2

MOV.w #0x0055,R5 does the following: src → dst

BIC.w #0xFFEE,R5 does the following not.src .and. dst → dst not.src .and. dst → dst

BIS.w #0x1144,R5 does the following: src .or. dst → dst src .or. dst → dst

Just look at the MSP 430 User Guide

BIS[.W] Set bits in destination BIS.B
Set bits in destination

Syntax BIS src,dst or
BIS.W src,dst BIS.B src,dst

Operation src .OR. dst −> dst

Description The source operand and the destination operand are logically ORed. The result is placed into the destination. The source operand is not affected.

Status Bits Status bits are not affected.

Mode Bits OSCOFF, CPUOFF, and GIE are not affected.

Example The six LSBs of the RAM word TOM are set.

BIS #003Fh,TOM; set the six LSBs in RAM location TOM

Example The three MSBs of RAM byte TOM are set.

BIS.B #0E0h,TOM ; set the 3 MSBs in RAM location TOM

Of Course:

BIC[.W] Clear bits in destination BIC.B
Clear bits in destination

Syntax BIC src,dst or
BIC.W src,dst BIC.B src,dst

Operation .NOT.src .AND. dst −> dst

Description The inverted source operand and the destination operand are logically ANDed. The result is placed into the destination. The source operand is not affected.

Status Bits Status bits are not affected.

Mode Bits OSCOFF, CPUOFF, and GIE are not affected.

Example The six MSBs of the RAM word LEO are cleared.

BIC #0FC00h,LEO ; Clear 6 MSBs in MEM(LEO)

Example The five MSBs of the RAM byte LEO are cleared.

BIC.B #0F8h,LEO ; Clear 5 MSBs in Ram location LEO

I was able to find this user guide with a related link on this very website

Answer 3

A piece of information missing from the existing answers is the significance of .W vs .B.

From Section 3.4 of the MSP430F24x User Guide (SLAU144J) on page 56 it specifies,

B/W:

Byte or word operation:

0: word operation

1: byte operation

It is worth noting that the default is that instructions operate on a word.