I currently try to understand how exactly the platform initialization works on modern UEFI x86 systems. However, it is unclear how the privilege modes ...

I'm trying to read the LLC cache miss hardware counter in a Linux kernel module on an Intel Xeon gold (Skylake generation) processor. The result of th ...

I am trying to set way masks for different class of service (COS) on an Intel Xeon processor. I am using the following command to make COS0 use all bu ...

I am trying to download the history messages for a specific Slack app, let's say MLflow. I found a few open-source tools on Github but none of them a ...

How can I retrieve all commits that changed files with one or two kinds of extensions, e.g. ".YAML" and ".JSON"? ...

How to search Git commit messages (not diffs) in a software repository with regular expression and output those messages & their line number to a ...

First of all, I do not know whether I should be asking this here or in the Electronics StackExchange, so please let me know if you think I should ask ...

I have searched Intel manual Vol.4. MSR 0x1a4 can control L1 cache prefetcher and L2 cache prefetcher, but I just want to disable L3 cache prefetcher. ...

Intel sometimes uses the MSR_ prefix for MSR names, and sometimes IA32_, even for the same MSR. For example, on SNB, in SDM Volume 4, they document b ...

As part of a build process, I want to run the following two commands: This sets the /dev/cpu/*/msr files exposed by the msr kernel module to world- ...

I have disabled hardware prefetching using the following guidelines: Installed msr-tools 1.3 The prefetcher information for my system (Broadwell) i ...

I am trying to disable hardware prefetching on my machine: CPU family: 6 Model: 78 Model name: Intel(R) Core(TM) i5-6200U CPU @ 2.30GHz I have che ...

I am using perf to monitor the system for certain events. However, I get the following error and I have no idea where it comes from,as the event is li ...

I am trying to check if a bit is clear in IA32_VMX_EPT_VPID_CAP (48CH) but in some cases I am working with hardware that dose not have that msr(q9300) ...

Every modern high-performance CPU of the x86/x86_64 architecture has some hierarchy of data caches: L1, L2, and sometimes L3 (and L4 in very rare case ...

I want to modify "Core Clock Frequency to System Bus Frequency Ratio BITS[31:24]" in register MSR_EBC_FREQUENCY_ID (0x2C) on Pentium 4 desktop process ...

I was working on msr registers to manipulate processor frequency to save power to one of our research project for HPC Systems. I have done following: ...

I installed perf on Haswell CPU( Intel Core i7-4790 ). But the "perf list" does not include "stalled-cycles-frontend" nor "stalled-cycles-backend". I ...

I'm trying to make a kernel module to enable FOP compatibility mode for x87 FPU. This is done via setting bit 2 in IA32_MISC_ENABLE MSR. Here's the co ...

I have the following environment: ubuntu 12.04 kernel 3.2.0-29-generic-pae all installed on parallels version 11.0.1. I have installed msr-tools using ...