紧凑型 1 位 ALU 行为中的问题
[英]Issues in compact 1-bit ALU behavior
问题描述
我试图为一个实现逻辑运算、一个全加器和一个全减法器的 1 位 ALU 编写一个紧凑的代码。 编译看起来不错，但它没有断言消息"Test done." 在测试台的末尾。 而且，A、B、F等变量中的逻辑值的变化应该会导致测试台出错，对程序来说是不变的，因为它不会报告任何错误。 主要设计肯定有问题，但我找不到问题。
在测试台上，我只是测试了每个function的一些案例。
library IEEE;
use IEEE.std_logic_1164.all;
entity ALU is
port(A,B : in bit; -- operands
S : in bit_vector(2 downto 0);
F: out bit; -- output
carryIn: in bit;
carryOut: out bit);
end ALU;
architecture behavior of ALU is
begin
process(S)
begin
case (S) is
when "000" => if carryIn = '1' then F <= A XOR B XOR carryIn; -- Full Adder
carryOut <= (A AND B) OR (carryIn AND A) OR (carryIn AND B);
end if;
when "001" => if carryIn = '1' then F <= (A XOR B) XOR carryIn; -- Full Subtractor
carryOut <= ((NOT A) AND (B OR carryIn)) OR (B AND carryIn);
end if;
when "010" => F <= A AND B;
when "011" => F <= A OR B;
when "100" => F <= A NAND B;
when "101" => F <= A NOR B;
when "110" => F <= A XOR B;
when "111" => F <= A XNOR B;
end case;
end process;
end behavior ;
试验台
library IEEE;
use IEEE.std_logic_1164.all;
entity testbench is
end testbench;
architecture tb of testbench is
component ALU is
port(A,B : in bit;
S : in bit_vector(2 downto 0);
F: out bit;
carryIn: in bit;
carryOut: out bit);
end component;
signal A, B, F, carryIn, carryOut: bit;
signal S : bit_vector(2 downto 0);
begin
DUT: ALU port map (A => A, B => B, F => F, carryIn => carryIn, carryOut => carryOut, S => S);
process
begin
-- AND
S <= "010";
A <= '0';
B <= '0';
carryIn <= '0';
assert(F ='0' and carryOut = '0') report "Fail AND1" severity error;
wait;
S <= "010";
A <= '0';
B <= '1';
carryIn <= '0';
assert(F ='0' and carryOut = '0') report "Fail AND2" severity error;
wait;
-- OR
S <= "011";
A <= '0';
B <= '0';
carryIn <= '0';
assert(F ='0' and carryOut = '0') report "Fail OR1" severity error;
wait;
S <= "011";
A <= '0';
B <= '1';
carryIn <= '0';
assert(F ='1' and carryOut = '0') report "Fail OR2" severity error;
wait;
-- NAND
S <= "100";
A <= '0';
B <= '0';
carryIn <= '0';
assert(F ='1' and carryOut = '0') report "Fail NAND1" severity error;
wait;
S <= "100";
A <= '1';
B <= '1';
carryIn <= '0';
assert(F ='0' and carryOut = '0') report "Fail NAND2" severity error;
wait;
-- NOR
S <= "101";
A <= '0';
B <= '0';
carryIn <= '0';
assert(F ='1' and carryOut = '0') report "Fail NOR1" severity error;
wait;
S <= "101";
A <= '1';
B <= '0';
carryIn <= '0';
assert(F ='0' and carryOut = '0') report "Fail NOR2" severity error;
wait;
-- XOR
S <= "110";
A <= '0';
B <= '1';
carryIn <= '0';
assert(F ='1' and carryOut = '0') report "Fail XOR1" severity error;
wait;
S <= "110";
A <= '1';
B <= '0';
carryIn <= '0';
assert(F ='1' and carryOut = '0') report "Fail XOR2" severity error;
wait;
-- XNOR
S <= "111";
A <= '0';
B <= '1';
carryIn <= '0';
assert(F ='0' and carryOut = '0') report "Fail XNOR1" severity error;
wait;
S <= "111";
A <= '1';
B <= '0';
carryIn <= '0';
assert(F ='0' and carryOut = '0') report "Fail XNOR2" severity error;
wait;
-- Full Adder
S <= "000";
A <= '0';
B <= '0';
carryIn <= '1';
assert(F ='1' and carryOut = '0') report "Fail FullAdder1" severity error;
wait;
S <= "000";
A <= '1';
B <= '1';
carryIn <= '1';
assert(F ='1' and carryOut = '1') report "Fail FullAdder2" severity error;
wait;
-- Full Subtractor
S <= "000";
A <= '0';
B <= '1';
carryIn <= '1';
assert(F ='0' and carryOut = '1') report "Fail Subtractor1" severity error;
wait;
S <= "000";
A <= '1';
B <= '1';
carryIn <= '1';
assert(F ='1' and carryOut = '1') report "Fail Subtractor2" severity error;
wait;
assert false report "Test done." severity note;
wait;
end process;
end tb;
编辑
library IEEE;
use IEEE.std_logic_1164.all;
entity testbench is
end testbench;
architecture tb of testbench is
component ALU is
port(A,B : in bit;
S : in bit_vector(2 downto 0);
F: out bit;
carryIn: in bit;
carryOut: out bit);
end component;
signal A, B, F, carryIn, carryOut: bit;
signal S : bit_vector(2 downto 0);
begin
DUT: ALU port map (A => A, B => B, F => F, carryIn => carryIn, carryOut => carryOut, S => S);
process
begin
-- AND
S <= "010";
A <= '0';
B <= '0';
wait for 20 ns;
assert(F ='0') report "Fail AND1" severity error;
wait for 20 ns;
S <= "010";
A <= '0';
B <= '1';
assert(F ='0') report "Fail AND2" severity error;
wait for 20 ns;
-- OR
S <= "011";
A <= '0';
B <= '0';
wait for 20 ns;
assert(F ='0') report "Fail OR1" severity error;
wait for 20 ns;
S <= "011";
A <= '0';
B <= '1';
wait for 20 ns;
assert(F ='1') report "Fail OR2" severity error;
wait for 20 ns;
-- NAND
S <= "100";
A <= '0';
B <= '0';
wait for 20 ns;
assert(F ='1') report "Fail NAND1" severity error;
wait for 20 ns;
S <= "100";
A <= '1';
B <= '1';
wait for 20 ns;
assert(F ='0') report "Fail NAND2" severity error;
wait for 20 ns;
-- NOR
S <= "101";
A <= '0';
B <= '0';
wait for 20 ns;
assert(F ='1') report "Fail NOR1" severity error;
wait for 20 ns;
S <= "101";
A <= '1';
B <= '0';
wait for 20 ns;
assert(F ='0') report "Fail NOR2" severity error;
wait for 20 ns;
-- XOR
S <= "110";
A <= '0';
B <= '1';
wait for 20 ns;
assert(F ='1') report "Fail XOR1" severity error;
wait for 20 ns;
S <= "110";
A <= '1';
B <= '0';
wait for 20 ns;
assert(F ='1') report "Fail XOR2" severity error;
wait for 20 ns;
-- XNOR
S <= "111";
A <= '0';
B <= '1';
wait for 20 ns;
assert(F ='0') report "Fail XNOR1" severity error;
wait for 20 ns;
S <= "111";
A <= '1';
B <= '0';
wait for 20 ns;
assert(F ='0') report "Fail XNOR2" severity error;
wait for 20 ns;
-- Full Adder
S <= "000";
A <= '0';
B <= '0';
carryIn <= '1';
wait for 20 ns;
assert(F ='1') report "Fail FullAdder1" severity error;
wait for 20 ns;
S <= "000";
A <= '1';
B <= '1';
carryIn <= '1';
wait for 20 ns;
assert(F ='1') report "Fail FullAdder2" severity error;
wait for 20 ns;
-- Full Subtractor
S <= "000";
A <= '0';
B <= '1';
carryIn <= '1';
wait for 20 ns;
assert(F ='0') report "Full Subtractor 1" severity error;
wait for 20 ns;
S <= "000";
A <= '1';
B <= '1';
carryIn <= '1';
wait for 20 ns;
assert(F ='1') report "Full Subtractor 2" severity error;
wait for 20 ns;
assert false report "Test done." severity note;
wait;
end process;
end tb;
在当前程序中，我遇到了以下执行错误：
# EXECUTION:: ERROR : Fail OR2
# EXECUTION:: Time: 120 ns, Iteration: 0, Instance: /testbench,
Process: line__21.
# EXECUTION:: ERROR : Fail NAND2
# EXECUTION:: Time: 200 ns, Iteration: 0, Instance: /testbench,
Process: line__21.
# EXECUTION:: ERROR : Fail NOR2
# EXECUTION:: Time: 280 ns, Iteration: 0, Instance: /testbench,
Process: line__21.
# EXECUTION:: ERROR : Fail Subtrator1
# EXECUTION:: Time: 560 ns, Iteration: 0, Instance: /testbench,
Process: line__21.
# EXECUTION:: NOTE : Test done.
# EXECUTION:: Time: 620 ns, Iteration: 0, Instance: /testbench,
Process: line__21.
# KERNEL: Simulation has finished. There are no more test vectors to
simulate.
# VSIM: Simulation has finished.
它似乎与主程序有关，但我不确定为什么它会显示这些错误，因为测试台中的逻辑似乎是正确的。
我还更改了以下部分
when "000" => F <= A XOR B XOR carryIn; -- Full Adder
carryOut <= (A AND B) OR (carryIn
AND A) OR (carryIn AND B);
when "001" => F <= (A XOR B) XOR carryIn; -- Full Subtractor
carryOut <= ((NOT A) AND (B OR
carryIn)) OR (B AND carryIn);
然后在测试台中获取进位。
2 个解决方案
解决方案1
0 2021-12-01 15:25:40
首先，您architecture behavior of ALU过程存在问题：
该过程应对所有输入敏感，而不仅仅是
S：process(S, A, B, carryIn)这样，如果
S没有变化，但输入数据发生变化，则重新计算输出，而不是保持其先前的值。carryOut应始终分配一个值，而不仅仅是在算术运算时。 否则，当您尝试合成它时，您将推断出锁存器来存储其值。对于 model 的加法和减法，只有在
carryIn = '1'的情况下。 其他情况呢？
所有问题的解决方案示例：
```vhdl
process(S, A, B, carryIn)
begin
carryOut <= '0';
case (S) is
when "000" => -- Full Adder
F <= A XOR B XOR carryIn;
carryOut <= (A AND B) OR (carryIn AND A) OR (carryIn AND B);
when "001" => -- Full Subtractor
F <= A XOR B XOR carryIn;
carryOut <= ((NOT A) AND (B OR carryIn)) OR (B AND carryIn);
when "010" => F <= A AND B;
when "011" => F <= A OR B;
when "100" => F <= A NAND B;
when "101" => F <= A NOR B;
when "110" => F <= A XOR B;
when others => F <= A XNOR B;
end case;
end process;
```
（注意when others使用时，保证我们不忘单例）。
然后你的模拟环境也有问题。 你写了：
process
begin
-- AND
S <= "010";
A <= '0';
B <= '0';
carryIn <= '0';
assert(F ='0' and carryOut = '0') report "Fail AND1" severity error;
wait;
...
这不起作用有两个原因：您在测试向量产生任何效果之前检查它的效果。 由于信号分配和断言之间没有时间流逝，因此F和carryOut值还没有改变。 您检查它们在输入更改之前的值。
第二个问题是wait; 意味着永远等待。 它肯定会暂停你的进程。 其他语句将永远不会执行，并且模拟将停止，因为在您的情况下没有其他事情要做。
要解决这两个问题，请编写：
process
begin
-- AND
S <= "010";
A <= '0';
B <= '0';
carryIn <= '0';
wait for 1 ns;
assert (F = '0') and (carryOut = '0') report "Fail AND1" severity error;
S <= "010";
A <= '0';
B <= '1';
carryIn <= '0';
wait for 1 ns;
assert (F = '0') and (carryOut = '0') report "Fail AND2" severity error;
...
请注意，您可以通过不重新分配不变的信号来简化一点：
process
begin
-- AND
S <= "010";
A <= '0';
B <= '0';
carryIn <= '0';
wait for 1 ns;
assert (F = '0') and (carryOut = '0') report "Fail AND1" severity error;
B <= '1';
wait for 1 ns;
assert (F = '0') and (carryOut = '0') report "Fail AND2" severity error;
...
最后一点：VHDL 是一种高级编程语言。 您可以使用它的一些功能来简化您的测试平台。 例如，您可以使用ieee.numeric_bit_unsigned package，它允许对向量进行算术运算以及向量和整数之间的转换。 类似的东西（未测试）：
...
use ieee.numeric_bit_unsigned.all;
...
process
begin
for i in 0 to 7 loop -- loop over the 8 possible values of (A,B,carryIn)
(A, B, carryIn) <= to_bitvector(i, 3);
-- AND
S <= "010";
wait for 1 ns;
assert F = ((A and B)) and (carryOut = '0') report "Fail AND" severity error;
-- OR
S <= "011";
wait for 1 ns;
assert (F = (A or B)) and (carryOut = '0') report "Fail OR" severity error;
...
...
-- Full Adder
S <= "000";
wait for 1 ns;
assert carryOut & f = ('0' & A) + ('0' & B) + carryIn
report "Fail FullAdder" severity error;
-- full subtractor
S <= "001";
wait for 1 ns;
assert carryOut & F = ('0' & A) - (('0' & B) + carryIn)
report "Fail FullSubtractor" severity error;
end loop;
assert false report "Test done." severity note;
wait;
end process;
解决方案2
0 2021-12-01 17:55:29
这反映了在赏金和您的编辑之前评论中建议的更改。
空格和可选关键字已用于显示代码组织。
更改的基本原理如下。
library IEEE;
use IEEE.std_logic_1164.all;
entity ALU is
port (
A, B: in bit; -- operands
S: in bit_vector(2 downto 0);
F: out bit; -- output
carryIn: in bit;
carryOut: out bit
);
end entity ALU;
architecture behavior of ALU is
begin
-- process (S)
process (S, A, B, carryIn) -- CHANGED - ADDED A, B, carryIn Tarick Welling
begin
carryOut <= '0'; -- CHANGED - ADDED DEFAULT ASSIGNMENT user16145658
case (S) is
when "000" =>
-- if carryIn = '1' then -- CHANGED not needed user16145658
F <= A XOR B XOR carryIn; -- Full Adder
carryOut <= (A AND B) OR (carryIn AND A) OR (carryIn AND B);
-- end if; -- CHANGED not needed user16145658
when "001" =>
-- if carryIn = '1' then -- CHANGED not needed user16145658
F <= (A XOR B) XOR carryIn; -- Full Subtractor
carryOut <= ((NOT A) AND (B OR carryIn)) OR (B AND carryIn);
-- end if; -- CHANGED not needed user16145658
when "010" =>
F <= A AND B;
when "011" =>
F <= A OR B;
when "100" =>
F <= A NAND B;
when "101" =>
F <= A NOR B;
when "110" =>
F <= A XOR B;
when "111" =>
F <= A XNOR B;
end case;
end process;
end architecture behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity testbench is
end testbench;
architecture tb of testbench is
component ALU is
port (
A, B: in bit;
S: in bit_vector(2 downto 0);
F: out bit;
carryIn: in bit;
carryOut: out bit
);
end component ALU;
signal A, B, F, carryIn, carryOut: bit;
signal S: bit_vector(2 downto 0);
begin
DUT:
ALU
port map (
A => A,
B => B,
F => F,
carryIn => carryIn,
carryOut => carryOut,
S => S
);
process
begin
-- AND
S <= "010";
A <= '0';
B <= '0';
carryIn <= '0';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='0' and carryOut = '0'
report "Fail AND1"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
S <= "010";
A <= '0';
B <= '1';
carryIn <= '0';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='0' and carryOut = '0'
report "Fail AND2"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
-- OR
S <= "011";
A <= '0';
B <= '0';
carryIn <= '0';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='0' and carryOut = '0'
report "Fail OR1"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
S <= "011";
A <= '0';
B <= '1';
carryIn <= '0';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='1' and carryOut = '0'
report "Fail OR2"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
-- NAND
S <= "100";
A <= '0';
B <= '0';
carryIn <= '0';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='1' and carryOut = '0'
report "Fail NAND1"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
S <= "100";
A <= '1';
B <= '1';
carryIn <= '0';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='0' and carryOut = '0'
report "Fail NAND2"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
-- NOR
S <= "101";
A <= '0';
B <= '0';
carryIn <= '0';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='1' and carryOut = '0'
report "Fail NOR1"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
S <= "101";
A <= '1';
B <= '0';
carryIn <= '0';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='0' and carryOut = '0'
report "Fail NOR2"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
-- XOR
S <= "110";
A <= '0';
B <= '1';
carryIn <= '0';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='1' and carryOut = '0'
report "Fail XOR1"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
S <= "110";
A <= '1';
B <= '0';
carryIn <= '0';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='1' and carryOut = '0'
report "Fail XOR2"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
-- XNOR
S <= "111";
A <= '0';
B <= '1';
carryIn <= '0';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='0' and carryOut = '0'
report "Fail XNOR1"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
S <= "111";
A <= '1';
B <= '0';
carryIn <= '0';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='0' and carryOut = '0'
report "Fail XNOR2"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
-- Full Adder
S <= "000";
A <= '0';
B <= '0';
carryIn <= '1';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='1' and carryOut = '0'
report "Fail FullAdder1"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
S <= "000";
A <= '1';
B <= '1';
carryIn <= '1';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='1' and carryOut = '1'
report "Fail FullAdder2"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
-- Full Subtractor
S <= "000";
A <= '0';
B <= '1';
carryIn <= '1';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='0' and carryOut = '1'
report "Fail Subtractor1"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
S <= "000";
A <= '1';
B <= '1';
carryIn <= '1';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='1' and carryOut = '1'
report "Fail Subtractor2"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
assert false
report "Test done."
severity note;
wait; -- KEEP AS IS user16145658
end process;
end architecture tb;
这产生了 output：
/usr/local/bin/ghdl -r testbench --wave=testbench.ghw
testbench.vhdl:232:9:@320ns:(assertion note): Test done.
没有所有的断言测试错误报告。
（报告语句的格式特定于 VHDL 实现。）
过程敏感度列表
过程敏感性仅包含S 。 这使得正确的模拟取决于刺激顺序。 它还在综合中推断锁存器，这里S用作锁存其他评估输入值的使能。 由于两个原因，不希望出现闩锁。 在合成硬件中，它们占用可用于有意设计规范的资源，更糟糕的是会导致模拟和实现行为之间的不匹配（这里通过依赖于 OR1 和 OR2 之间显示的刺激顺序等）。
过程敏感度列表的规则可在 IEEE Std 1076 中找到，此处使用修订版 -2008。 （没有发现完全符合 -2008 的 VHDL 语言的实现，也没有人声称遵守后来的 -2019 修订版。）
11.3 工艺说明：
如果在保留字 process 之后出现进程敏感度列表，则假定进程语句包含隐式等待语句作为进程语句部分的最后一条语句； 这个隐式等待语句的形式是
等待敏感列表；
...
如果在进程语句中的保留字process之后出现进程敏感度列表，则进程语句不应包含显式等待语句。 类似地，如果这样的流程语句是过程的父过程，那么如果该过程包含等待语句，则它是错误的。
...
转至 10.2 等待声明：
敏感度子句定义了等待语句的敏感度集，即等待语句对其敏感的信号集。 敏感度列表中的每个信号名称都将给定信号标识为敏感度集的成员。 灵敏度列表中的每个信号名称应为 static 信号名称，每个名称应表示允许读取的信号。 ...
由于等待语句的敏感度集中的任何信号上发生事件，挂起的进程也会恢复。 如果发生此类事件，则评估条件子句中的条件。 ...
由于等待语句的敏感度集中的任何信号上发生事件，挂起的进程也会恢复。
进程在等待语句中挂起和恢复，这里是由于敏感列表中列出的信号上的事件。
回到 11.3：
流程语句的执行包括重复执行其语句序列。 在执行流程语句的语句序列中的最后一条语句后，将立即继续执行语句序列中的第一条语句。
合成的敏感性列表如下。
对 carryOut 的默认分配
修复敏感度列表揭示了另一个刺激顺序依赖性，导致在carryOut上的锁存。
在 IEEE Std 1076.6-2004 RTL Synthesis 中可以找到关于如何推断锁存器的最清晰描述（由于年龄和缺乏维护而撤回）。
6.2.1.1 带有敏感列表的进程的级别敏感存储：
当满足以下所有条件时，应为信号（或变量）建模电平敏感存储元件：
a) 信号（或变量）有明确的赋值。
b) 信号（或变量）没有以 <clock_edge> 为条件的执行路径。
c) 有一些进程执行不执行对信号（或变量）的显式赋值（通过赋值语句）。
默认情况下，信号（或变量）的身份分配的效果应该就像分配不存在一样。
...过程敏感度列表应包含在过程声明中读取的所有信号。
目的是使仿真行为与综合设计规范行为相匹配。
Tarick Welling 应该建议将过程中读取的所有信号添加到过程灵敏度列表中。
从 ALU 中删除 if 语句加减选择
carryIn在生成赋值给F和carryOut的值的表达式中进行评估。 通过使用 if 语句进行条件执行所施加的限制是不兼容的。
在测试台进程中移动等待语句
当任何进程正在运行或尚未恢复时，不会发生信号更新。 信号更新在模拟周期中比恢复和随后暂停过程更早应用：
14.7.5 Model 执行
14.7.5.1 概述
model 的执行包括一个初始化阶段，然后是重复执行该 model 描述中的流程语句。 每一次这样的重复都被称为一个模拟循环。 在每个循环中，计算描述中所有信号的值。 如果该计算的结果是在给定信号上发生事件，则对该信号敏感的过程语句将恢复并作为模拟周期的一部分执行。
等待语句需要超时子句的原因见 10.2 等待语句：
timeout 子句指定进程将在此等待语句处保持挂起的最长时间。 如果没有出现超时子句，则假定为 (STD.STANDARD.TIME'HIGH – STD.STANDARD.NOW) 的超时子句。 如果 timeout 子句中的时间表达式的计算结果为负值，则会出错。
其中 TIME'HIGH 是最大模拟时间，表示模拟将结束。 基本上没有超时子句，您就用完了模拟时钟。
如何排除故障
您有经验的读者阅读了您的代码并注意到了这些 model 缺点。 否则，您可以使用彻底的测试台刺激，可能会重新安排以确定发生了什么。 您会发现，可能使用波形显示，您的代码忽略了输入，而S没有改变（NOR1 到 NOR 2 等）。 在过程敏感度列表中找不到这些输入。
摆脱闩锁取决于了解其原因。 通过提供彻底的测试刺激可以看到效果。
由于对刺激顺序的敏感性，敏感性列表问题可能需要的不仅仅是彻底的测试刺激。 （这里以前的“测试向量”为carryOut提供了一个无害的值，您可以正确地测试它的值。）
1位ALU图的组件
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