緊湊型 1 位 ALU 行為中的問題
[英]Issues in compact 1-bit ALU behavior
問題描述
我試圖為一個實現邏輯運算、一個全加器和一個全減法器的 1 位 ALU 編寫一個緊湊的代碼。 編譯看起來不錯，但它沒有斷言消息"Test done." 在測試台的末尾。 而且，A、B、F等變量中的邏輯值的變化應該會導致測試台出錯，對程序來說是不變的，因為它不會報告任何錯誤。 主要設計肯定有問題，但我找不到問題。
在測試台上，我只是測試了每個function的一些案例。
library IEEE;
use IEEE.std_logic_1164.all;
entity ALU is
port(A,B : in bit; -- operands
S : in bit_vector(2 downto 0);
F: out bit; -- output
carryIn: in bit;
carryOut: out bit);
end ALU;
architecture behavior of ALU is
begin
process(S)
begin
case (S) is
when "000" => if carryIn = '1' then F <= A XOR B XOR carryIn; -- Full Adder
carryOut <= (A AND B) OR (carryIn AND A) OR (carryIn AND B);
end if;
when "001" => if carryIn = '1' then F <= (A XOR B) XOR carryIn; -- Full Subtractor
carryOut <= ((NOT A) AND (B OR carryIn)) OR (B AND carryIn);
end if;
when "010" => F <= A AND B;
when "011" => F <= A OR B;
when "100" => F <= A NAND B;
when "101" => F <= A NOR B;
when "110" => F <= A XOR B;
when "111" => F <= A XNOR B;
end case;
end process;
end behavior ;
試驗台
library IEEE;
use IEEE.std_logic_1164.all;
entity testbench is
end testbench;
architecture tb of testbench is
component ALU is
port(A,B : in bit;
S : in bit_vector(2 downto 0);
F: out bit;
carryIn: in bit;
carryOut: out bit);
end component;
signal A, B, F, carryIn, carryOut: bit;
signal S : bit_vector(2 downto 0);
begin
DUT: ALU port map (A => A, B => B, F => F, carryIn => carryIn, carryOut => carryOut, S => S);
process
begin
-- AND
S <= "010";
A <= '0';
B <= '0';
carryIn <= '0';
assert(F ='0' and carryOut = '0') report "Fail AND1" severity error;
wait;
S <= "010";
A <= '0';
B <= '1';
carryIn <= '0';
assert(F ='0' and carryOut = '0') report "Fail AND2" severity error;
wait;
-- OR
S <= "011";
A <= '0';
B <= '0';
carryIn <= '0';
assert(F ='0' and carryOut = '0') report "Fail OR1" severity error;
wait;
S <= "011";
A <= '0';
B <= '1';
carryIn <= '0';
assert(F ='1' and carryOut = '0') report "Fail OR2" severity error;
wait;
-- NAND
S <= "100";
A <= '0';
B <= '0';
carryIn <= '0';
assert(F ='1' and carryOut = '0') report "Fail NAND1" severity error;
wait;
S <= "100";
A <= '1';
B <= '1';
carryIn <= '0';
assert(F ='0' and carryOut = '0') report "Fail NAND2" severity error;
wait;
-- NOR
S <= "101";
A <= '0';
B <= '0';
carryIn <= '0';
assert(F ='1' and carryOut = '0') report "Fail NOR1" severity error;
wait;
S <= "101";
A <= '1';
B <= '0';
carryIn <= '0';
assert(F ='0' and carryOut = '0') report "Fail NOR2" severity error;
wait;
-- XOR
S <= "110";
A <= '0';
B <= '1';
carryIn <= '0';
assert(F ='1' and carryOut = '0') report "Fail XOR1" severity error;
wait;
S <= "110";
A <= '1';
B <= '0';
carryIn <= '0';
assert(F ='1' and carryOut = '0') report "Fail XOR2" severity error;
wait;
-- XNOR
S <= "111";
A <= '0';
B <= '1';
carryIn <= '0';
assert(F ='0' and carryOut = '0') report "Fail XNOR1" severity error;
wait;
S <= "111";
A <= '1';
B <= '0';
carryIn <= '0';
assert(F ='0' and carryOut = '0') report "Fail XNOR2" severity error;
wait;
-- Full Adder
S <= "000";
A <= '0';
B <= '0';
carryIn <= '1';
assert(F ='1' and carryOut = '0') report "Fail FullAdder1" severity error;
wait;
S <= "000";
A <= '1';
B <= '1';
carryIn <= '1';
assert(F ='1' and carryOut = '1') report "Fail FullAdder2" severity error;
wait;
-- Full Subtractor
S <= "000";
A <= '0';
B <= '1';
carryIn <= '1';
assert(F ='0' and carryOut = '1') report "Fail Subtractor1" severity error;
wait;
S <= "000";
A <= '1';
B <= '1';
carryIn <= '1';
assert(F ='1' and carryOut = '1') report "Fail Subtractor2" severity error;
wait;
assert false report "Test done." severity note;
wait;
end process;
end tb;
編輯
library IEEE;
use IEEE.std_logic_1164.all;
entity testbench is
end testbench;
architecture tb of testbench is
component ALU is
port(A,B : in bit;
S : in bit_vector(2 downto 0);
F: out bit;
carryIn: in bit;
carryOut: out bit);
end component;
signal A, B, F, carryIn, carryOut: bit;
signal S : bit_vector(2 downto 0);
begin
DUT: ALU port map (A => A, B => B, F => F, carryIn => carryIn, carryOut => carryOut, S => S);
process
begin
-- AND
S <= "010";
A <= '0';
B <= '0';
wait for 20 ns;
assert(F ='0') report "Fail AND1" severity error;
wait for 20 ns;
S <= "010";
A <= '0';
B <= '1';
assert(F ='0') report "Fail AND2" severity error;
wait for 20 ns;
-- OR
S <= "011";
A <= '0';
B <= '0';
wait for 20 ns;
assert(F ='0') report "Fail OR1" severity error;
wait for 20 ns;
S <= "011";
A <= '0';
B <= '1';
wait for 20 ns;
assert(F ='1') report "Fail OR2" severity error;
wait for 20 ns;
-- NAND
S <= "100";
A <= '0';
B <= '0';
wait for 20 ns;
assert(F ='1') report "Fail NAND1" severity error;
wait for 20 ns;
S <= "100";
A <= '1';
B <= '1';
wait for 20 ns;
assert(F ='0') report "Fail NAND2" severity error;
wait for 20 ns;
-- NOR
S <= "101";
A <= '0';
B <= '0';
wait for 20 ns;
assert(F ='1') report "Fail NOR1" severity error;
wait for 20 ns;
S <= "101";
A <= '1';
B <= '0';
wait for 20 ns;
assert(F ='0') report "Fail NOR2" severity error;
wait for 20 ns;
-- XOR
S <= "110";
A <= '0';
B <= '1';
wait for 20 ns;
assert(F ='1') report "Fail XOR1" severity error;
wait for 20 ns;
S <= "110";
A <= '1';
B <= '0';
wait for 20 ns;
assert(F ='1') report "Fail XOR2" severity error;
wait for 20 ns;
-- XNOR
S <= "111";
A <= '0';
B <= '1';
wait for 20 ns;
assert(F ='0') report "Fail XNOR1" severity error;
wait for 20 ns;
S <= "111";
A <= '1';
B <= '0';
wait for 20 ns;
assert(F ='0') report "Fail XNOR2" severity error;
wait for 20 ns;
-- Full Adder
S <= "000";
A <= '0';
B <= '0';
carryIn <= '1';
wait for 20 ns;
assert(F ='1') report "Fail FullAdder1" severity error;
wait for 20 ns;
S <= "000";
A <= '1';
B <= '1';
carryIn <= '1';
wait for 20 ns;
assert(F ='1') report "Fail FullAdder2" severity error;
wait for 20 ns;
-- Full Subtractor
S <= "000";
A <= '0';
B <= '1';
carryIn <= '1';
wait for 20 ns;
assert(F ='0') report "Full Subtractor 1" severity error;
wait for 20 ns;
S <= "000";
A <= '1';
B <= '1';
carryIn <= '1';
wait for 20 ns;
assert(F ='1') report "Full Subtractor 2" severity error;
wait for 20 ns;
assert false report "Test done." severity note;
wait;
end process;
end tb;
在當前程序中，我遇到了以下執行錯誤：
# EXECUTION:: ERROR : Fail OR2
# EXECUTION:: Time: 120 ns, Iteration: 0, Instance: /testbench,
Process: line__21.
# EXECUTION:: ERROR : Fail NAND2
# EXECUTION:: Time: 200 ns, Iteration: 0, Instance: /testbench,
Process: line__21.
# EXECUTION:: ERROR : Fail NOR2
# EXECUTION:: Time: 280 ns, Iteration: 0, Instance: /testbench,
Process: line__21.
# EXECUTION:: ERROR : Fail Subtrator1
# EXECUTION:: Time: 560 ns, Iteration: 0, Instance: /testbench,
Process: line__21.
# EXECUTION:: NOTE : Test done.
# EXECUTION:: Time: 620 ns, Iteration: 0, Instance: /testbench,
Process: line__21.
# KERNEL: Simulation has finished. There are no more test vectors to
simulate.
# VSIM: Simulation has finished.
它似乎與主程序有關，但我不確定為什么它會顯示這些錯誤，因為測試台中的邏輯似乎是正確的。
我還更改了以下部分
when "000" => F <= A XOR B XOR carryIn; -- Full Adder
carryOut <= (A AND B) OR (carryIn
AND A) OR (carryIn AND B);
when "001" => F <= (A XOR B) XOR carryIn; -- Full Subtractor
carryOut <= ((NOT A) AND (B OR
carryIn)) OR (B AND carryIn);
然后在測試台中獲取進位。
2 個解決方案
解決方案1
0 2021-12-01 15:25:40
首先，您architecture behavior of ALU過程存在問題：
該過程應對所有輸入敏感，而不僅僅是
S：process(S, A, B, carryIn)這樣，如果
S沒有變化，但輸入數據發生變化，則重新計算輸出，而不是保持其先前的值。carryOut應始終分配一個值，而不僅僅是在算術運算時。 否則，當您嘗試合成它時，您將推斷出鎖存器來存儲其值。對於 model 的加法和減法，只有在
carryIn = '1'的情況下。 其他情況呢？
所有問題的解決方案示例：
```vhdl
process(S, A, B, carryIn)
begin
carryOut <= '0';
case (S) is
when "000" => -- Full Adder
F <= A XOR B XOR carryIn;
carryOut <= (A AND B) OR (carryIn AND A) OR (carryIn AND B);
when "001" => -- Full Subtractor
F <= A XOR B XOR carryIn;
carryOut <= ((NOT A) AND (B OR carryIn)) OR (B AND carryIn);
when "010" => F <= A AND B;
when "011" => F <= A OR B;
when "100" => F <= A NAND B;
when "101" => F <= A NOR B;
when "110" => F <= A XOR B;
when others => F <= A XNOR B;
end case;
end process;
```
（注意when others使用時，保證我們不忘單例）。
然后你的模擬環境也有問題。 你寫了：
process
begin
-- AND
S <= "010";
A <= '0';
B <= '0';
carryIn <= '0';
assert(F ='0' and carryOut = '0') report "Fail AND1" severity error;
wait;
...
這不起作用有兩個原因：您在測試向量產生任何效果之前檢查它的效果。 由於信號分配和斷言之間沒有時間流逝，因此F和carryOut值還沒有改變。 您檢查它們在輸入更改之前的值。
第二個問題是wait; 意味着永遠等待。 它肯定會暫停你的進程。 其他語句將永遠不會執行，並且模擬將停止，因為在您的情況下沒有其他事情要做。
要解決這兩個問題，請編寫：
process
begin
-- AND
S <= "010";
A <= '0';
B <= '0';
carryIn <= '0';
wait for 1 ns;
assert (F = '0') and (carryOut = '0') report "Fail AND1" severity error;
S <= "010";
A <= '0';
B <= '1';
carryIn <= '0';
wait for 1 ns;
assert (F = '0') and (carryOut = '0') report "Fail AND2" severity error;
...
請注意，您可以通過不重新分配不變的信號來簡化一點：
process
begin
-- AND
S <= "010";
A <= '0';
B <= '0';
carryIn <= '0';
wait for 1 ns;
assert (F = '0') and (carryOut = '0') report "Fail AND1" severity error;
B <= '1';
wait for 1 ns;
assert (F = '0') and (carryOut = '0') report "Fail AND2" severity error;
...
最后一點：VHDL 是一種高級編程語言。 您可以使用它的一些功能來簡化您的測試平台。 例如，您可以使用ieee.numeric_bit_unsigned package，它允許對向量進行算術運算以及向量和整數之間的轉換。 類似的東西（未測試）：
...
use ieee.numeric_bit_unsigned.all;
...
process
begin
for i in 0 to 7 loop -- loop over the 8 possible values of (A,B,carryIn)
(A, B, carryIn) <= to_bitvector(i, 3);
-- AND
S <= "010";
wait for 1 ns;
assert F = ((A and B)) and (carryOut = '0') report "Fail AND" severity error;
-- OR
S <= "011";
wait for 1 ns;
assert (F = (A or B)) and (carryOut = '0') report "Fail OR" severity error;
...
...
-- Full Adder
S <= "000";
wait for 1 ns;
assert carryOut & f = ('0' & A) + ('0' & B) + carryIn
report "Fail FullAdder" severity error;
-- full subtractor
S <= "001";
wait for 1 ns;
assert carryOut & F = ('0' & A) - (('0' & B) + carryIn)
report "Fail FullSubtractor" severity error;
end loop;
assert false report "Test done." severity note;
wait;
end process;
解決方案2
0 2021-12-01 17:55:29
這反映了在賞金和您的編輯之前評論中建議的更改。
空格和可選關鍵字已用於顯示代碼組織。
更改的基本原理如下。
library IEEE;
use IEEE.std_logic_1164.all;
entity ALU is
port (
A, B: in bit; -- operands
S: in bit_vector(2 downto 0);
F: out bit; -- output
carryIn: in bit;
carryOut: out bit
);
end entity ALU;
architecture behavior of ALU is
begin
-- process (S)
process (S, A, B, carryIn) -- CHANGED - ADDED A, B, carryIn Tarick Welling
begin
carryOut <= '0'; -- CHANGED - ADDED DEFAULT ASSIGNMENT user16145658
case (S) is
when "000" =>
-- if carryIn = '1' then -- CHANGED not needed user16145658
F <= A XOR B XOR carryIn; -- Full Adder
carryOut <= (A AND B) OR (carryIn AND A) OR (carryIn AND B);
-- end if; -- CHANGED not needed user16145658
when "001" =>
-- if carryIn = '1' then -- CHANGED not needed user16145658
F <= (A XOR B) XOR carryIn; -- Full Subtractor
carryOut <= ((NOT A) AND (B OR carryIn)) OR (B AND carryIn);
-- end if; -- CHANGED not needed user16145658
when "010" =>
F <= A AND B;
when "011" =>
F <= A OR B;
when "100" =>
F <= A NAND B;
when "101" =>
F <= A NOR B;
when "110" =>
F <= A XOR B;
when "111" =>
F <= A XNOR B;
end case;
end process;
end architecture behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity testbench is
end testbench;
architecture tb of testbench is
component ALU is
port (
A, B: in bit;
S: in bit_vector(2 downto 0);
F: out bit;
carryIn: in bit;
carryOut: out bit
);
end component ALU;
signal A, B, F, carryIn, carryOut: bit;
signal S: bit_vector(2 downto 0);
begin
DUT:
ALU
port map (
A => A,
B => B,
F => F,
carryIn => carryIn,
carryOut => carryOut,
S => S
);
process
begin
-- AND
S <= "010";
A <= '0';
B <= '0';
carryIn <= '0';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='0' and carryOut = '0'
report "Fail AND1"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
S <= "010";
A <= '0';
B <= '1';
carryIn <= '0';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='0' and carryOut = '0'
report "Fail AND2"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
-- OR
S <= "011";
A <= '0';
B <= '0';
carryIn <= '0';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='0' and carryOut = '0'
report "Fail OR1"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
S <= "011";
A <= '0';
B <= '1';
carryIn <= '0';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='1' and carryOut = '0'
report "Fail OR2"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
-- NAND
S <= "100";
A <= '0';
B <= '0';
carryIn <= '0';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='1' and carryOut = '0'
report "Fail NAND1"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
S <= "100";
A <= '1';
B <= '1';
carryIn <= '0';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='0' and carryOut = '0'
report "Fail NAND2"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
-- NOR
S <= "101";
A <= '0';
B <= '0';
carryIn <= '0';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='1' and carryOut = '0'
report "Fail NOR1"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
S <= "101";
A <= '1';
B <= '0';
carryIn <= '0';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='0' and carryOut = '0'
report "Fail NOR2"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
-- XOR
S <= "110";
A <= '0';
B <= '1';
carryIn <= '0';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='1' and carryOut = '0'
report "Fail XOR1"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
S <= "110";
A <= '1';
B <= '0';
carryIn <= '0';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='1' and carryOut = '0'
report "Fail XOR2"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
-- XNOR
S <= "111";
A <= '0';
B <= '1';
carryIn <= '0';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='0' and carryOut = '0'
report "Fail XNOR1"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
S <= "111";
A <= '1';
B <= '0';
carryIn <= '0';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='0' and carryOut = '0'
report "Fail XNOR2"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
-- Full Adder
S <= "000";
A <= '0';
B <= '0';
carryIn <= '1';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='1' and carryOut = '0'
report "Fail FullAdder1"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
S <= "000";
A <= '1';
B <= '1';
carryIn <= '1';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='1' and carryOut = '1'
report "Fail FullAdder2"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
-- Full Subtractor
S <= "000";
A <= '0';
B <= '1';
carryIn <= '1';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='0' and carryOut = '1'
report "Fail Subtractor1"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
S <= "000";
A <= '1';
B <= '1';
carryIn <= '1';
wait for 20 ns; -- CHANGED MOVED user16145658
assert F ='1' and carryOut = '1'
report "Fail Subtractor2"
severity error;
-- wait for 20 ns; -- CHANGED MOVED added timeout clause mkrieger1
assert false
report "Test done."
severity note;
wait; -- KEEP AS IS user16145658
end process;
end architecture tb;
這產生了 output：
/usr/local/bin/ghdl -r testbench --wave=testbench.ghw
testbench.vhdl:232:9:@320ns:(assertion note): Test done.
沒有所有的斷言測試錯誤報告。
（報告語句的格式特定於 VHDL 實現。）
過程敏感度列表
過程敏感性僅包含S 。 這使得正確的模擬取決於刺激順序。 它還在綜合中推斷鎖存器，這里S用作鎖存其他評估輸入值的使能。 由於兩個原因，不希望出現閂鎖。 在合成硬件中，它們占用可用於有意設計規范的資源，更糟糕的是會導致模擬和實現行為之間的不匹配（這里通過依賴於 OR1 和 OR2 之間顯示的刺激順序等）。
過程敏感度列表的規則可在 IEEE Std 1076 中找到，此處使用修訂版 -2008。 （沒有發現完全符合 -2008 的 VHDL 語言的實現，也沒有人聲稱遵守后來的 -2019 修訂版。）
11.3 工藝說明：
如果在保留字 process 之后出現進程敏感度列表，則假定進程語句包含隱式等待語句作為進程語句部分的最后一條語句； 這個隱式等待語句的形式是
等待敏感列表；
...
如果在進程語句中的保留字process之后出現進程敏感度列表，則進程語句不應包含顯式等待語句。 類似地，如果這樣的流程語句是過程的父過程，那么如果該過程包含等待語句，則它是錯誤的。
...
轉至 10.2 等待聲明：
敏感度子句定義了等待語句的敏感度集，即等待語句對其敏感的信號集。 敏感度列表中的每個信號名稱都將給定信號標識為敏感度集的成員。 靈敏度列表中的每個信號名稱應為 static 信號名稱，每個名稱應表示允許讀取的信號。 ...
由於等待語句的敏感度集中的任何信號上發生事件，掛起的進程也會恢復。 如果發生此類事件，則評估條件子句中的條件。 ...
由於等待語句的敏感度集中的任何信號上發生事件，掛起的進程也會恢復。
進程在等待語句中掛起和恢復，這里是由於敏感列表中列出的信號上的事件。
回到 11.3：
流程語句的執行包括重復執行其語句序列。 在執行流程語句的語句序列中的最后一條語句后，將立即繼續執行語句序列中的第一條語句。
合成的敏感性列表如下。
對 carryOut 的默認分配
修復敏感度列表揭示了另一個刺激順序依賴性，導致在carryOut上的鎖存。
在 IEEE Std 1076.6-2004 RTL Synthesis 中可以找到關於如何推斷鎖存器的最清晰描述（由於年齡和缺乏維護而撤回）。
6.2.1.1 帶有敏感列表的進程的級別敏感存儲：
當滿足以下所有條件時，應為信號（或變量）建模電平敏感存儲元件：
a) 信號（或變量）有明確的賦值。
b) 信號（或變量）沒有以 <clock_edge> 為條件的執行路徑。
c) 有一些進程執行不執行對信號（或變量）的顯式賦值（通過賦值語句）。
默認情況下，信號（或變量）的身份分配的效果應該就像分配不存在一樣。
...過程敏感度列表應包含在過程聲明中讀取的所有信號。
目的是使仿真行為與綜合設計規范行為相匹配。
Tarick Welling 應該建議將過程中讀取的所有信號添加到過程靈敏度列表中。
從 ALU 中刪除 if 語句加減選擇
carryIn在生成賦值給F和carryOut的值的表達式中進行評估。 通過使用 if 語句進行條件執行所施加的限制是不兼容的。
在測試台進程中移動等待語句
當任何進程正在運行或尚未恢復時，不會發生信號更新。 信號更新在模擬周期中比恢復和隨后暫停過程更早應用：
14.7.5 Model 執行
14.7.5.1 概述
model 的執行包括一個初始化階段，然后是重復執行該 model 描述中的流程語句。 每一次這樣的重復都被稱為一個模擬循環。 在每個循環中，計算描述中所有信號的值。 如果該計算的結果是在給定信號上發生事件，則對該信號敏感的過程語句將恢復並作為模擬周期的一部分執行。
等待語句需要超時子句的原因見 10.2 等待語句：
timeout 子句指定進程將在此等待語句處保持掛起的最長時間。 如果沒有出現超時子句，則假定為 (STD.STANDARD.TIME'HIGH – STD.STANDARD.NOW) 的超時子句。 如果 timeout 子句中的時間表達式的計算結果為負值，則會出錯。
其中 TIME'HIGH 是最大模擬時間，表示模擬將結束。 基本上沒有超時子句，您就用完了模擬時鍾。
如何排除故障
您有經驗的讀者閱讀了您的代碼並注意到了這些 model 缺點。 否則，您可以使用徹底的測試台刺激，可能會重新安排以確定發生了什么。 您會發現，可能使用波形顯示，您的代碼忽略了輸入，而S沒有改變（NOR1 到 NOR 2 等）。 在過程敏感度列表中找不到這些輸入。
擺脫閂鎖取決於了解其原因。 通過提供徹底的測試刺激可以看到效果。
由於對刺激順序的敏感性，敏感性列表問題可能需要的不僅僅是徹底的測試刺激。 （這里以前的“測試向量”為carryOut提供了一個無害的值，您可以正確地測試它的值。）
1位ALU圖的組件
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