在VHDL中實現32位ALU

Question

我正在VHDL中實現32位ALU。 我發現一個錯誤。 我不明白為什么我得到這個..這是無法更新'in'對象out_alu

 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 ----==== Entity of AlU with input and Output 
 entity AlU is  Port (
   A : in  STD_LOGIC_VECTOR (31 downto 0);       ---== A input   Vector with 32 Bit 
   B : in  STD_LOGIC_VECTOR (31 downto 0);       ---== B input   Vector with 32 Bit 
   S : in  STD_LOGIC_VECTOR (2 downto 0) ;       ---== S select  Input Vector 3 bit for operation  
   out_AlU : in  STD_LOGIC_VECTOR (31 downto 0));---== Output of AlU 32 
 end AlU;

 architecture Behavioral of AlU is
 begin

 Select_for_operation: Process (S)   ---= Deffierent  Process for AlU with the     selection of S
                  begin
                                Case S is  
                                when     "000" =>  
                                          out_AlU <=A xor  B ;
                                when   "001"=> 
                                          out_AlU <=A Xnor B ;
                                when   "100"=> 
                                          out_AlU <=A  or  B ; 
                                when   "101"=> 
                                         out_AlU  <=A  nor B ;
                                when   "110"=> 
                                         out_AlU  <=A  and B ;
                                when    others => 
                                                    NULL ;      
                                end case ;
                        end Process ;
 end Behavioral;

Answer 1

您的信號out_ALU被聲明為您實體的輸入。 這就是為什么您不能為其分配信號的原因（可以這么說，它是只讀的）。

將其更改為out，可能會編譯為：

 entity AlU is  Port (
   A : in  STD_LOGIC_VECTOR (31 downto 0);       ---== A input   Vector with 32 Bit 
   B : in  STD_LOGIC_VECTOR (31 downto 0);       ---== B input   Vector with 32 Bit 
   S : in  STD_LOGIC_VECTOR (2 downto 0) ;       ---== S select  Input Vector 3 bit for operation  
   out_AlU : out  STD_LOGIC_VECTOR (31 downto 0));---== Output of AlU 32 
 end AlU;