VHDL測試台不更改輸出ALU 32位

Question

您看，我已經完成了用modelsim描述vhdl上的ALU，但是測試台似乎沒有更新解決方案，當我看到仿真時，電路的32位響應總是說"UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU"我不知道我寫錯了什么在測試台上，編譯器上還會有關於電路響應的警告，內容為

**警告：（vsim-8683）未初始化的輸出端口/ alu_tb / ALU_test / res（32降至0）沒有驅動程序。 該端口將為信號網絡貢獻價值（UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU）。

這是測試平台代碼：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ALU_tb is        
end ALU_tb;

architecture bhv_ALU_tb of ALU_tb is
component ALU
    port(
        a, b: in std_logic_vector(31 downto 0);
        c: in std_logic;
        s: in std_logic_vector(3 downto 0);
        res: out std_logic_vector(32 downto 0));
end component;

signal a, b: std_logic_vector(31 downto 0);
signal c: std_logic;
signal s: std_logic_vector(3 downto 0);
signal re: std_logic_vector(32 downto 0);

begin 
    ALU_test: ALU port map (a => a, b => b, c => c, s => s, res => re);
process begin
    b <= "00000000000010100111010100011110";
    a <= "00000000011010000100110011101110";
    c <= '0';
    s <= "1111";
    wait for 2 ns;
    b <= "00000000000010100111010100011110";
    a <= "00000000011010000100110011101110";
    c <= '0';
    s <= "0100";
    wait for 2 ns;
    s <= "0000";
    wait for 2 ns;
    s <= "0001";
    wait for 2 ns;
    s <= "0010";
    wait for 2 ns;
    s <= "0011";
    wait for 2 ns;
    s <= "0100";
    wait for 2 ns;
    s <= "0101";
    wait for 2 ns;
    s <= "0110";
    wait for 2 ns;
    s <= "0111";
    wait for 2 ns;
    s <= "1000";
    wait for 2 ns;
    s <= "1001";
    wait for 2 ns;
    s <= "1010";
    wait for 2 ns;
    s <= "1011";
    wait for 2 ns;
    s <= "1100";
    wait for 2 ns;
    s <= "1101";
    wait for 2 ns;
    s <= "1110";
    wait for 2 ns;
    s <= "1111";
    wait for 2 ns;
end process;
end bhv_ALU_tb;

我知道該錯誤似乎是微不足道的“ res未初始化”，但我距vhdl的時間太長了，老實說不知道如何解決它，有什么想法嗎？

Answer 1

首先

use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

不好..不要使用。 您甚至在此文件中都不需要它們。 如果您需要算術，請使用numeric_std 。

然后：錯誤在於組件ALU ，因為應該“驅動” res 。 但是由於您尚未發布該代碼，因此我們無法為您提供幫助。

ps當前，您不再需要在VHDL中定義組件。 您可以這樣寫：

ALU_test: entity work.ALU port map