使用同步D觸發器進行4位傳輸（從寄存器a到寄存器b傳輸4位）

Question

運行此代碼時，出現兩個錯誤，提示“端口映射中的實際參數類型與正式端口的類型不匹配。我需要幫助以了解如何解決這些問題。

-- code that try in EDA playground to transfer from one register to another 

 -- library 
 library ieee;
 use ieee. std_logic_1164.all;


 -- declaration for d flip-flop
 entity D_FF is
 PORT( D : in std_logic_vector(7 downto 0);
       s :in std_logic; 
       CLOCK: in std_logic;
       Q: out std_logic_vector(7 downto 0));
  end D_FF;

 architecture behavioral of D_FF is
 -- signals declaration
 signal s1,s2,s3,s4,s5,s6,s7,s8: std_logic;
 begin

 --transfer the 4 bit to another register
s1 <= D(0) and (not s);
Q(0) <= s and D(0);
s2 <= D(1) and (not s);
Q(1) <= (Q(0)and s) or s2;
s3 <= D(2) and (not s);
Q(2) <= (Q(1)and s) or s3;
s4 <= D(3) and not s;
Q(3) <= (Q(2)and s)or s4;
s5 <= D(4) and not s;
Q(4) <= (Q(3)and s)or s5;
s6 <= D(5) and not s;
Q(5) <= (Q(4)and s)or s6;
s7 <= D(6) and not s;
Q(6) <= (Q(5)and s)or s7;
s8 <= D(7) and not s;
Q(7) <= (Q(6)and s)or s8;

end behavioral;

 ------------------------------
-- testbench
 ------------------------------
 -- library
library ieee;
use ieee. std_logic_1164.all;


entity testbench is 
-- empty entity
end testbench;
-----------------------------
architecture tb of testbench is -- testbench 
-- architecture  -- REDUNDANT transcription error?
 -- component declaration
 component D_FF is
 PORT( D : in std_logic_vector(7 downto 0);
       s :in std_logic;
       CLOCK: in std_logic;
       Q: out std_logic_vector(7 downto 0));
  end component;

  -- signals that need in testbench -- COMMENT DELIMITER transcription error?
  signal D_s: std_logic_vector(7 downto 0);-- signals for entity i/o
  signal Q_s: std_logic_vector(7 downto 0);-- signals for entity i/o
  signal s_s: std_logic;
  signal CLOCK_s: std_logic;
  -- is the signal that must be run 4 time to transfer the bit 
  signal loop_count: integer;
   begin

  dut:D_FF port map(D_s,Q_s,s_s,CLOCK_s);   
  -- design under test instantiation

 stimProcess: process                                           -- 
 --stimulus generator
  begin
    --the run 4 time this to transfer the 4 bit 
    for loop_counter in 0 to 3 loop
    D_s <= "01100000";
    wait until CLOCK_s = '1' and CLOCK_s'event;
    end loop;

  end process stimProcess;                                  
  -- without sensitivity list
  end tb;

Answer 1

您正在使用位置關聯的端口圖。 執行此操作時，端口映射中的端口順序必須與組件聲明中的端口順序匹配。 使用位置關聯，正確的順序是：

dut:D_FF port map(D_s,s_s,CLOCK_s,Q_s); 

請注意，在你的榜樣，您已經連接信號Q_s到s ， s_s到CLOCK ，並CLOCK_s到Q （因為你的順序是不一樣的）。

我總是喜歡命名關聯。 在左側，您擁有“正式”（組件聲明中概述的端口）。 在右側，您具有“實際”（連接到該端口的信號）。 空格只是為了提高可讀性。

dut: D_FF 
  port map (
    D     => D_s,
    s     => s_s,
    CLOCK => CLOCK_s,
    Q     => Q_s
  );

命名關聯端口映射更容易調試，並且可以按任何順序映射端口。