[英]4bit transfer using synchronous d flip-flop( transfer 4bit from register a to register b)
When I run this code two errors appear that say "Actual parameter type in port map does not match the type of the formal port 's'. I need help to understand how to fix these. 运行此代码时,出现两个错误,提示“端口映射中的实际参数类型与正式端口的类型不匹配。我需要帮助以了解如何解决这些问题。
-- code that try in EDA playground to transfer from one register to another
-- library
library ieee;
use ieee. std_logic_1164.all;
-- declaration for d flip-flop
entity D_FF is
PORT( D : in std_logic_vector(7 downto 0);
s :in std_logic;
CLOCK: in std_logic;
Q: out std_logic_vector(7 downto 0));
end D_FF;
architecture behavioral of D_FF is
-- signals declaration
signal s1,s2,s3,s4,s5,s6,s7,s8: std_logic;
begin
--transfer the 4 bit to another register
s1 <= D(0) and (not s);
Q(0) <= s and D(0);
s2 <= D(1) and (not s);
Q(1) <= (Q(0)and s) or s2;
s3 <= D(2) and (not s);
Q(2) <= (Q(1)and s) or s3;
s4 <= D(3) and not s;
Q(3) <= (Q(2)and s)or s4;
s5 <= D(4) and not s;
Q(4) <= (Q(3)and s)or s5;
s6 <= D(5) and not s;
Q(5) <= (Q(4)and s)or s6;
s7 <= D(6) and not s;
Q(6) <= (Q(5)and s)or s7;
s8 <= D(7) and not s;
Q(7) <= (Q(6)and s)or s8;
end behavioral;
------------------------------
-- testbench
------------------------------
-- library
library ieee;
use ieee. std_logic_1164.all;
entity testbench is
-- empty entity
end testbench;
-----------------------------
architecture tb of testbench is -- testbench
-- architecture -- REDUNDANT transcription error?
-- component declaration
component D_FF is
PORT( D : in std_logic_vector(7 downto 0);
s :in std_logic;
CLOCK: in std_logic;
Q: out std_logic_vector(7 downto 0));
end component;
-- signals that need in testbench -- COMMENT DELIMITER transcription error?
signal D_s: std_logic_vector(7 downto 0);-- signals for entity i/o
signal Q_s: std_logic_vector(7 downto 0);-- signals for entity i/o
signal s_s: std_logic;
signal CLOCK_s: std_logic;
-- is the signal that must be run 4 time to transfer the bit
signal loop_count: integer;
begin
dut:D_FF port map(D_s,Q_s,s_s,CLOCK_s);
-- design under test instantiation
stimProcess: process --
--stimulus generator
begin
--the run 4 time this to transfer the 4 bit
for loop_counter in 0 to 3 loop
D_s <= "01100000";
wait until CLOCK_s = '1' and CLOCK_s'event;
end loop;
end process stimProcess;
-- without sensitivity list
end tb;
You are using a positional association for the port map. 您正在使用位置关联的端口图。 When you do this, the order of ports in your port map must match the order of ports in your component declaration.
执行此操作时,端口映射中的端口顺序必须与组件声明中的端口顺序匹配。 Using positional association, the proper order is:
使用位置关联,正确的顺序是:
dut:D_FF port map(D_s,s_s,CLOCK_s,Q_s);
Note that in your example, you've connected the signal Q_s
to s
, s_s
to CLOCK
, and CLOCK_s
to Q
(because your order was not the same). 请注意,在你的榜样,您已经连接信号
Q_s
到s
, s_s
到CLOCK
,并CLOCK_s
到Q
(因为你的顺序是不一样的)。
I always prefer named association. 我总是喜欢命名关联。 On the left, you have your "formal" (the port outlined in your component declaration).
在左侧,您拥有“正式”(组件声明中概述的端口)。 On the right, you have the "actual" (the signal you're connecting to that port).
在右侧,您具有“实际”(连接到该端口的信号)。 The whitespace is just to improve readability.
空格只是为了提高可读性。
dut: D_FF
port map (
D => D_s,
s => s_s,
CLOCK => CLOCK_s,
Q => Q_s
);
Named association port maps are much easier to debug, and the ports can be mapped in any order. 命名关联端口映射更容易调试,并且可以按任何顺序映射端口。
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