带 D 触发器的结构 4 位环形计数器。 VHDL / GHDL

Question

I don't know how to do this with structural programming...

"A binary counter (with reset signal) of 4 bits made of 4 D flip flops."

How to connect in/outs?

Here is the entity declarations. The core of the problem is at the last lines.

                    --FFD
            entity FFD is
            port( CLK, D, reset : in STD_LOGIC;
                Q : out STD_LOGIC
               );
            end FFD;
            
            architecture behaviour of FFD is
            begin
                process(CLK, reset)
                begin
                if reset='1' then Q<='0';  
                elsif (clk'event and clk='1') then Q<=D;
                else null;
                end if;
                end process;
            end behaviour;
        ----------------------------------------------------------  
            
        --counter

        library IEEE;
        use IEEE.std_logic_1164.all;
        use IEEE.numeric_std.all;

            entity counter is
            port(clk : in std_logic;
               reset : in std_logic;
               count : out std_logic_vector(3 downto 0));
            end entity counter;

                architecture rtl of counter is
            
            --
            component FFD 
            port (CLK, D, reset : in STD_LOGIC;
                       Q : out STD_LOGIC);
            end component;
            
            signal q0,q1,q2: std_logic:='0';
            signal q3: std_logic:='1';
            
            begin
            -- 

            ---
            inst1: FFD port map (CLK=>clk, D=>q3, reset=>reset, Q=>q0);
            inst2: FFD port map (CLK=>clk, D=>q0, reset=>reset, Q=>q1);
            inst3: FFD port map (CLK=>clk, D=>q1, reset=>reset, Q=>q2);
            inst4: FFD port map (CLK=>clk, D=>q2, reset=>reset, Q=>q3);
            inst5: count<=q3&q2&q1&q0;
            end architecture rtl;

My problem is in this last lines.

Answer 1

There's no issue with your connections (they correctly form a ring counter), but you're not going to see much happen. After reset, all of your flip-flops contain zero, which will get circulated around the ring with each clock pulse but never actually cause a change in the outputs. The assignment of a default value of '1' for q3 when you declare the signal will be overridden by the actual output of the flip-flop as soon as your circuit starts operating (or simulating), and is generally the wrong way to initialize hardware.

You need to insure that when you assert the reset signal, your hardware transitions into an appropriate state (ie: one bit set, all others clear). One way to do this would be to use a FF with a set input for Q3. If you don't have a flip flop that with a set (instead of a reset) signal, you can simulate one by putting inverters on the input and output, which will provide a '1' to be clocked around your ring counter when you apply reset. You could also create some intermediate signals and craft a multiplexer for the D inputs to build a loadable counter, or any of a variety of other solutions...

Answer 2

I think the problem is somewhere else.

I think your D flip flop output Q should have port direction as inout(or buffer) and not out. This is because the output is also acting as input. i think this must be carefully watched while doing structural modeling.

port (CLK, D, reset : in STD_LOGIC; Q : inout STD_LOGIC);

but please check i am not sure,

johnson counter is also ring counter, see this VHDL code for Johnson Counter which is using structural modeling style