[英]D Flip Flop in VHDL
I'm trying to implement a D Flip Flop in VHDL, using a D Latch I wrote.我正在尝试使用我编写的 D Latch 在 VHDL 中实现 D 触发器。 But there seems to be an error with the clock, and I can't figure out what that is.但是时钟似乎有错误,我无法弄清楚那是什么。
Here is the code for my D Latch.这是我的 D Latch 的代码。
Library ieee;
Use ieee.std_logic_1164.all;
entity d_latch is
port (c,d : in std_logic;
q,nq : out std_logic);
end d_latch;
architecture arch of d_latch is
Signal qt, nqt: std_logic;
begin
qt <= (d nand c) nand nqt;
nqt <= ((not d) nand c) nand qt;
q <= qt;
nq <= nqt;
end arch;
I tested it and it works, and here is the code for my d flip flop:我测试了它并且它有效,这是我的 d 触发器的代码:
Library ieee;
Use ieee.std_logic_1164.all;
entity d_flipflop is
port (d,clock : in std_logic;
q,nq : out std_logic);
end d_flipflop;
architecture arch of d_flipflop is
Component d_latch
Port
(
d, clk: in std_logic;
q, nq : out std_logic
);
End Component ;
Signal qt, nqt: std_logic;
begin
dl1: d_latch port map (
d => d,
clk => not clock,
q => qt
);
dl2: d_latch port map (
d => qt,
clk => clock,
q => q,
nq => nq
);
end arch;
and here is the error:这是错误:
** Error: /home/devplayer/CSC343/Lab_2_Content/d_flipflop.vhd(25): (vcom-1436) Use of non globally static actual (prefix expression) of formal "clk" requires VHDL 2008.
Thank you谢谢
You cannot use full expressions in port assignments.您不能在端口分配中使用完整的表达式。 Instead of inverting the clock when assigning it to the port for your dl1 instance, create an inverted clock and use that:不要在将时钟分配给 dl1 实例的端口时反转时钟,而是创建一个反转时钟并使用它:
clockn <= not clock;
dl1: d_latch port map (
d => d,
clk => clockn,
q => qt
);
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