[英]Testbench for T Flip Flop using D Flip Flop in VHDL
I have VHDL codes that of a D Flip Flop, and a T Flip Flop that uses it structurally: it consists of a DFF with D input being T Xored with Q, a clock. 我有一个VHDL代码,一个D触发器和一个在结构上使用它的T触发器:它由DFF组成,D输入的T与Q或X时钟成对。 But my simulation gives me a waveform that has an output of only a red straight line 'U'. 但是我的仿真给了我一个仅输出红色直线“ U”的波形。 I think it is because of the feedback from Q to D, and is uninitialized at the beginning. 我认为这是因为从Q到D的反馈,并且一开始是未初始化的。 But I don't know how to write it otherwise. 但是我不知道怎么写。 This is the code: 这是代码:
--This is the DFF: -这是DFF:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity d_flip_flop is
port(
clk : in STD_LOGIC;
din : in STD_LOGIC;
reset : in STD_LOGIC;
dout : out STD_LOGIC
);
end d_flip_flop;
architecture d_flip_flop_arc of d_flip_flop is
begin
dff : process (din,clk,reset) is
begin
if (reset='1') then
dout <= '0';
elsif (rising_edge (clk)) then
dout <= din;
end if;
end process dff;
end d_flip_flop_arc;
--TFF: --TFF:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity tff_using_dff is
port(
clk : in STD_LOGIC;
t : in STD_LOGIC;
reset : in STD_LOGIC;
dout : out STD_LOGIC
);
end tff_using_dff;
architecture tff_using_dff_arc of tff_using_dff is
component d_flip_flop is
port(
clk : in STD_LOGIC;
din : in STD_LOGIC;
reset : in STD_LOGIC;
dout : out STD_LOGIC
);
end component d_flip_flop;
signal ip : std_logic;
signal op : std_logic;
begin
ip <= op xor t ;
u0 : d_flip_flop port map (clk => clk,
din => ip,
reset => reset,
dout => op);
dout <= op;
end tff_using_dff_arc;
--and current testbench: -和当前的测试台:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity T_FF_tb is
end T_FF_tb;
architecture T_FF_tb of T_FF_tb is
component tff_using_dff is
port(
clk : in STD_LOGIC;
t : in STD_LOGIC;
reset : in STD_LOGIC;
dout : out STD_LOGIC
);
end component;
signal clk,t,reset: std_logic:='0';
signal dout: std_logic:='0';
begin
U0: tff_using_dff port map(clk,t,reset,dout);
clk<=not clk after 5 ns;
t<= not t after 30 ns;
end T_FF_tb;
Your 'U' is caused by the output of the D flip flop being used in a combinatorial expression without being reset to a known state. 您的“ U”是由D触发器的输出在组合表达式中使用而未重置为已知状态引起的。
The simplest way to get the D flip flop buried in the T flip flop entity reset to a known would be to add a second process to the test bench along the lines: 将D触发器掩埋在T触发器实体中重置为已知的最简单方法是沿测试线在测试台上添加第二个过程:
RESET_PROC:
process
begin
wait for 5 ns;
reset <= '1';
wait for 5 ns;
reset <= '0';
wait;
end process;
An alternative to strobing the reset
signal in your test bench (which should be done anyways), you could define the initial state of the d_flip_flop
output. 除了选通测试台中的reset
信号(无论如何应这样做)的另一种方法,您可以定义d_flip_flop
输出的初始状态。 This can be done by defining an interim signal dout_i
for the register's output with an initial state assignment. 这可以通过使用初始状态分配为寄存器的输出定义一个临时信号dout_i
来完成。 Eg 例如
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity d_flip_flop is
port(
clk : in STD_LOGIC;
din : in STD_LOGIC;
reset : in STD_LOGIC;
dout : out STD_LOGIC
);
end d_flip_flop;
architecture d_flip_flop_arc of d_flip_flop is
signal dout_i : STD_LOGIC := '0';
begin
dff : process (clk,reset) is
begin
if (reset='1') then
dout_i <= '0';
elsif (rising_edge (clk)) then
dout_i <= din;
end if;
end process dff;
dout <= dout_i;
end d_flip_flop_arc;
This should achieve the same desired effect. 这应该达到相同的期望效果。 It also has the added bonus of making d_flip_flop
a little more robust. 它还具有使d_flip_flop
更加健壮的额外好处。
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