[英]T Flip Flop with clear (VHDL)
I'm having problems coding a T Flip Flop with clear and reset. 我在用清除和重置编码T触发器时遇到问题。 As the picture below shows, t_in is operating as enable input, that will be set to 1 or 0 from a mod-m counter.
如下图所示,t_in用作使能输入,将从mod-m计数器设置为1或0。 to_ldspkr will then toggle.
然后to_ldspkr将切换。 The clr_FF will clear the flip flop.
clr_FF将清除触发器。
Link to the block diagram 链接到框图
I'm now sure how I should code this flip flop. 我现在确定应该如何编写此触发器。 This is my code, but it's not working:
这是我的代码,但是不起作用:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity T_FF is
port(
from_t_in : in std_logic;
clk, reset : in std_logic;
from_clr_FF : in std_logic;
to_ldspkr : out std_logic
);
end T_FF;
architecture Behavioral of T_FF is
signal temp: std_logic;
signal r_reg, r_next : std_logic;
begin
process(reset, clk, from_clr_FF, r_reg)
begin
if(reset = '1') then
r_reg <= '0';
elsif(from_clr_FF = '1') then
r_next <= '0';
elsif(clk'event and clk='1') then
if(from_t_in = '1') then
temp <= not temp;
end if;
end if;
end process;
to_ldspkr <= temp;
end Behavioral;
temp is not initialized. temp未初始化。 I guess you don't need r_reg and r_next.
我猜您不需要r_reg和r_next。 Just replace them with temp, so it gets initialized on the reset(s).
只需将它们替换为temp,即可在重置时对其进行初始化。 r_reg is not needed then in the sensitivity.
那么就不需要r_reg了。
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