T Flip Flop with clear (VHDL)

Question

I'm having problems coding a T Flip Flop with clear and reset. As the picture below shows, t_in is operating as enable input, that will be set to 1 or 0 from a mod-m counter. to_ldspkr will then toggle. The clr_FF will clear the flip flop.

Link to the block diagram

I'm now sure how I should code this flip flop. This is my code, but it's not working:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity T_FF is
    port(
        from_t_in : in std_logic;
        clk, reset : in std_logic;
        from_clr_FF : in std_logic;
        to_ldspkr : out std_logic
    );
end T_FF;

architecture Behavioral of T_FF is
    signal temp: std_logic;
    signal r_reg, r_next : std_logic;

    begin
    process(reset, clk, from_clr_FF, r_reg)
    begin
        if(reset = '1') then
            r_reg <= '0';   
        elsif(from_clr_FF = '1') then
            r_next  <= '0';
        elsif(clk'event and clk='1') then
            if(from_t_in = '1') then
                temp <= not temp;
            end if;
        end if;
    end process;
    to_ldspkr <= temp;
end Behavioral;

Answer 1

temp is not initialized. I guess you don't need r_reg and r_next. Just replace them with temp, so it gets initialized on the reset(s). r_reg is not needed then in the sensitivity.