Do input and output ports in VHDL behave like flip-flops, ie are they updated on a rising or falling edge of a clock? Here is an example of what I mean.
entity main is
port(
clk : in std_logic; -- FPGA clock
x : in std_logic; -- input signal
y : out std_logic -- sampled input signal
);
end entity main;
architecture RTL of main is
signal y_q : std_logic;
begin
y <= y_q; -- set the output
copy : process(clk, x) is
variable y_d : std_logic;
begin
y_d := x; -- continuously sample x
if rising_edge(clk) then -- synchronous logic
y_q <= y_d; -- update flip-flop
end if;
end process copy;
end architecture RTL;
The program above simply samples the input signal x
, and sends it to the output y
. The signal y_q
is the sampled input signal x
, whereas a sample is taken on every rising edge of a clock clk
. However, I'm confused about the y
signal - is that signal completely the same as y_q
, or it is delayed by one clock cycle?
Because you asked. The code below is accepted by Intel/Altera and Xilinx synthesis.
entity main is
port(
clk : in std_logic; -- FPGA clock
x : in std_logic; -- input signal
y : out std_logic -- sampled input signal
);
end entity main;
architecture RTL of main is begin
y <= x when rising_edge(clk);
end architecture RTL;
Yes, you can use when
. You just cannot use it in a process before 2008.
As for you question, is signal y the same as signal y_q, the answer is YES. y <= y_q; is a cocurrent assignment out of any processes, it just says the two signals y and y_q should be connected together, so of course, they are the same.
You should not write a register in this style, although your code seems right logically. You could check xilinx XST user guide, it will tell you how to describe a few kinds of registers.
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