VHDL - Three layers of processes but no output from a logic unit in simulation

Question

My lab partner and I can't figure out why we're not getting any output in our waveform simulation of this component. We simulated the component by itself and obtained the expected behavior, but nested inside the entity, the output signal was not being initialized and only had uninitialized 'X' response.

This is the component declaration in the top level entity:

 99     component CH is
100     Port (  clk                 : in std_logic;
101                 X                   : in std_logic_vector(31 downto 0);
102                 Y                   : in std_logic_vector(31 downto 0);
103                 Z                   : in std_logic_vector(31 downto 0);    
104                 CH_OUT          : out std_logic_vector(31 downto 0)
105             );
106     end component;

This is the process we use to assign input/output:

289     round_compute2 : process (clk, CH_OUT_sig, e_sig, f_sig, g_sig, T1_sig)
290     begin
291             CH_X_in <= e_sig;
292             CH_Y_in <= f_sig;
293             CH_Z_in <= g_sig;
294             T1_sig <= std_logic_vector(unsigned(CH_OUT_sig));
295     end process;

This is the code for the CH component

  1 library IEEE;
  2 use IEEE.STD_LOGIC_1164.ALL;
  3 use IEEE.STD_LOGIC_ARITH.ALL;
  4 use IEEE.STD_LOGIC_UNSIGNED.ALL;
  5     
  6 -- CH is defined as (X AND Y) XOR (X' AND Z)
  7 -- Verified working
  8 
  9 entity CH is
 10     Port (  clk                 : in std_logic;
 11                 X                   : in std_logic_vector(31 downto 0);
 12                 Y                   : in std_logic_vector(31 downto 0);
 13                 Z                   : in std_logic_vector(31 downto 0);
 14                 CH_OUT          : out std_logic_vector(31 downto 0)
 15             );
 16 end CH;
 17 
 18 architecture Behavioral of CH is
 19 
 20 begin
 21 
 22     Compute : process (clk, X, Y, Z)
 23     begin
 24 
 25         CH_OUT <= (X and Y) xor ((not X) and Z);
 26 
 27     end process;
 28 
 29 end Behavioral;

These questions are similar, but do not address the issue in this post because-

VHDL component and outputs based on generic - Does not involve processes

Simple VHDL Problem with synchronous/asynchronous logic - Does not involve components and signals that are assigned from the system to the component

Why doesn't my code produce output? - Our code has the correct sensitivity list, I think

Answer 1

You should look through your tool's output for warnings. It sounds like you have an unbound component CH.

With:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--  3 use IEEE.STD_LOGIC_ARITH.ALL;
--  4 use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- CH is defined as (X AND Y) XOR (X' AND Z)
-- Verified working

entity CH is
    Port (  clk                 : in std_logic;
                 X                   : in std_logic_vector(31 downto 0);
                 Y                   : in std_logic_vector(31 downto 0);
                 Z                   : in std_logic_vector(31 downto 0);
                 CH_OUT          : out std_logic_vector(31 downto 0)
             );
end CH;

 architecture Behavioral of CH is

begin

Compute : process (clk, X, Y, Z)
    begin

        CH_OUT <= (X and Y) xor ((not X) and Z);

    end process;

end Behavioral;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ch_comp is
end entity;

architecture foo of ch_comp is

    component CH is
        Port (  clk                 : in std_logic;
                    X                   : in std_logic_vector(31 downto 0);
                    Y                   : in std_logic_vector(31 downto 0);
                    Z                   : in std_logic_vector(31 downto 0);    
                    CH_OUT          : out std_logic_vector(31 downto 0)
        );
    end component;

    signal CH_X_in:     std_logic_vector(31 downto 0);
    signal CH_Y_in:     std_logic_vector(31 downto 0);
    signal CH_Z_in:     std_logic_vector(31 downto 0);
    signal CH_OUT_sig:  std_logic_vector(31 downto 0);

    signal e_sig:       std_logic_vector(31 downto 0) := X"feedface";
    signal f_sig:       std_logic_vector(31 downto 0) := X"deadbeef";
    signal g_sig:       std_logic_vector(31 downto 0) := X"ffffffff";
    signal T1_sig:      std_logic_vector(31 downto 0);
    signal clk:         std_logic := '0';
begin

round_compute2 : process (clk, CH_OUT_sig, e_sig, f_sig, g_sig) --, T1_sig)
     begin
             CH_X_in <= e_sig;
             CH_Y_in <= f_sig;
             CH_Z_in <= g_sig;
             T1_sig <= std_logic_vector(unsigned(CH_OUT_sig));
     end process;

UUT:
    CH
        port map (
            clk => clk,
            X => CH_X_in,
            Y => CH_Y_in,
            Z => CH_Z_in,
            CH_OUT => CH_OUT_sig
        );
TEST:
    process
    begin
        wait for 10 ns;
        e_sig <= X"deadface";
        f_sig <= X"facebeef";
        g_sig <= X"EEEEFFFF";
        wait for 10 ns;
        wait;

    end process;

end architecture;

I got:

Which is to say, it appears not to exhibit only uninitialized 'X's on CH_out_sig or T1_sig.

And it would appear you haven't revealed either enough or your VHDL design description or enough of the tool build and simulation process for a third party to see where you went wrong.