[英]T flip flop VHDL code
I am learning VHDL and I ran into the following code: 我正在学习VHDL,遇到了以下代码:
Entity fft is
port (t, r: in bit; q: out bit);
End entity;
Architecture fft_df of fft is
signal state: bit :='0';
Begin
state <='0' when r='1' else
not state when t='0' and t'event else
state;
q<=state;
End;
Well, my doubt is about what this code does and if or not this is a behavioral or dataflow description of a T flip flop with reset. 好吧,我对此代码的作用感到怀疑,这是否是带复位的T触发器的行为或数据流描述。 And than, which is the meaning of not state when t='0' and t'event
? 并且,那么, not state when t='0' and t'event
, not state when t='0' and t'event
的含义是什么? (I suppose the T flip flop works on falling edge). (我想T触发器在下降沿工作)。
Thanks to all. 谢谢大家。
I'm missing the clock input. 我错过了时钟输入。 A T-flipflop (with asynchronous reset) would actually be described by T型触发器(具有异步复位)实际上是由
entity tff is
port (clk, reset, t: in bit; q: out bit);
end entity;
architecture rtl of tff is begin
q <= '0' when reset = '1' else
not q when rising_egde(clk) and t = '1';
end;
Or more commonly written as: 或更常用的写法是:
architecture rtl of tff is begin
tff_proc : process(clk, reset) begin
if reset = '1' then
q <= '0';
elsif rising_egde(clk) then
if t = '1' then
q <= not q;
end if;
end if;
end process;
end;
ps reading an output requires compiling in VHDL-2008 mode. ps读取输出需要在VHDL-2008模式下进行编译。
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