[英]Myhdl: assigning a bitslice to a signed variable fails with negative values
添加的代碼因 ValueError 而失敗,我不知道出了什么問題。 這是我想做的:在我的 fpga 中,我通過 spi 接收數據。 數據是到達 16 位寄存器 rxdata 的雙極性信號(在測量信號的意義上)。
任務是將這個信號解釋為有符號,並且只需要高 12 位(包括符號)。 因此,變量 bipolar 是 12 位寬和有符號的,即在代碼中聲明。 然后我分配:
bipolar.next=rxdata[:4].signed()
我的問題是,一旦數據變為負數(即最高有效位變為 1),12 位切片的分配就會失敗。
例如在運行時使用數據 0x8fff 我得到:
'ValueError:intbv 值 2303 >= 最大值 2048'
我不希望這樣,因為雙方都被聲明為簽名並且數據適合變量雙極。
還有另一種方法可以做到這一點嗎?
(順便說一句:bipolar[:].next=rxdata[:4].signed() 我得到 0 作為結果,我也不期望)
#testcase.py sk 09.12.2020
#assign a slice to a signed signal (bipolar) fails at runtime with negative numbers
from myhdl import *
nspi=16
n=12
tend=1e-6
@block
def testcase():
CLK = Signal(bool(0))
RESET = ResetSignal(1,active = 0, isasync=True)
bipolar=Signal(intbv(0,min=-2**(n-1),max=2**(n-1)))
rxdata = Signal(intbv(0)[nspi:0]) #received data is bipolar, transferred via spi into rxdata
''' Clock driver 16MHz'''
@always(delay(31))
def driver():
CLK.next = not CLK
@instance
def init():
rxdata.next=0x8fff #0x7fff i.e. positive passes, 0x8fff i.e negative fails runtime check
yield delay(100)
@always_seq(CLK.negedge,reset=RESET)
def assign():
#bipolar[:].next=rxdata[:(nspi-n)].signed() #this passes - but result is 0! (unexpected for me)
bipolar.next=rxdata[:(nspi-n)].signed() #this fails with negative numbers (unexpected for me)
print(bipolar, 'bipolar=', int(str(bipolar),16))
return instances()
tc = testcase()
tc.run_sim(tend*1e9)
print('Simulated to tend='+str(tend))
剛剛找到了方法:使用陰影信號。 即使用圓括號 () 而不是方括號..[]
#testcase.py sk 12.12.2020
#assign a slice to a signed signal (bipolar) fails at runtime with negative numbers
#-> use shadow signals instead! #bipolar[:].next=rxdata[:(nspi-n)].signed() #this passes - but result is 0! (unexpected for me)
from myhdl import *
nspi=16
n=12
tend=1e-6
@block
def testcase():
CLK = Signal(bool(0))
RESET = ResetSignal(1,active = 0, isasync=True)
bipolar=Signal(intbv(0,min=-2**(n-1),max=2**(n-1)))
#rxdata = Signal(intbv(0)[nspi:0]) #received data is bipolar, transferred via spi into rxdata
rxdata = Signal(intbv(0,min=0,max=2**nspi))
''' Clock driver 16MHz'''
@always(delay(31))
def driver():
CLK.next = not CLK
@instance
def init():
rxdata.next=0xffff #0x7fff i.e. positive passes, 0x8fff i.e negative fails runtime check when not using shadow
yield delay(100)
@always_seq(CLK.negedge,reset=RESET)
def assign():
#bipolar.next=rxdata[:(nspi-n)].signed() #this fails in runtime check -> number too big
#bipolar[:].next=rxdata[:(nspi-n)].signed() #this passes - but result is 0! (unexpected for me)
bipolar.next=rxdata(nspi,(nspi-n)).signed() #this is the way: use shadow signal !
print(bipolar, 'bipolar=', int(str(bipolar),16))
return instances()
tc = testcase()
tc.run_sim(tend*1e9)
print('Simulated to tend='+str(tend))
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