[英]Myhdl: assigning a bitslice to a signed variable fails with negative values
添加的代码因 ValueError 而失败,我不知道出了什么问题。 这是我想做的:在我的 fpga 中,我通过 spi 接收数据。 数据是到达 16 位寄存器 rxdata 的双极性信号(在测量信号的意义上)。
任务是将这个信号解释为有符号,并且只需要高 12 位(包括符号)。 因此,变量 bipolar 是 12 位宽和有符号的,即在代码中声明。 然后我分配:
bipolar.next=rxdata[:4].signed()
我的问题是,一旦数据变为负数(即最高有效位变为 1),12 位切片的分配就会失败。
例如在运行时使用数据 0x8fff 我得到:
'ValueError:intbv 值 2303 >= 最大值 2048'
我不希望这样,因为双方都被声明为签名并且数据适合变量双极。
还有另一种方法可以做到这一点吗?
(顺便说一句:bipolar[:].next=rxdata[:4].signed() 我得到 0 作为结果,我也不期望)
#testcase.py sk 09.12.2020
#assign a slice to a signed signal (bipolar) fails at runtime with negative numbers
from myhdl import *
nspi=16
n=12
tend=1e-6
@block
def testcase():
CLK = Signal(bool(0))
RESET = ResetSignal(1,active = 0, isasync=True)
bipolar=Signal(intbv(0,min=-2**(n-1),max=2**(n-1)))
rxdata = Signal(intbv(0)[nspi:0]) #received data is bipolar, transferred via spi into rxdata
''' Clock driver 16MHz'''
@always(delay(31))
def driver():
CLK.next = not CLK
@instance
def init():
rxdata.next=0x8fff #0x7fff i.e. positive passes, 0x8fff i.e negative fails runtime check
yield delay(100)
@always_seq(CLK.negedge,reset=RESET)
def assign():
#bipolar[:].next=rxdata[:(nspi-n)].signed() #this passes - but result is 0! (unexpected for me)
bipolar.next=rxdata[:(nspi-n)].signed() #this fails with negative numbers (unexpected for me)
print(bipolar, 'bipolar=', int(str(bipolar),16))
return instances()
tc = testcase()
tc.run_sim(tend*1e9)
print('Simulated to tend='+str(tend))
刚刚找到了方法:使用阴影信号。 即使用圆括号 () 而不是方括号..[]
#testcase.py sk 12.12.2020
#assign a slice to a signed signal (bipolar) fails at runtime with negative numbers
#-> use shadow signals instead! #bipolar[:].next=rxdata[:(nspi-n)].signed() #this passes - but result is 0! (unexpected for me)
from myhdl import *
nspi=16
n=12
tend=1e-6
@block
def testcase():
CLK = Signal(bool(0))
RESET = ResetSignal(1,active = 0, isasync=True)
bipolar=Signal(intbv(0,min=-2**(n-1),max=2**(n-1)))
#rxdata = Signal(intbv(0)[nspi:0]) #received data is bipolar, transferred via spi into rxdata
rxdata = Signal(intbv(0,min=0,max=2**nspi))
''' Clock driver 16MHz'''
@always(delay(31))
def driver():
CLK.next = not CLK
@instance
def init():
rxdata.next=0xffff #0x7fff i.e. positive passes, 0x8fff i.e negative fails runtime check when not using shadow
yield delay(100)
@always_seq(CLK.negedge,reset=RESET)
def assign():
#bipolar.next=rxdata[:(nspi-n)].signed() #this fails in runtime check -> number too big
#bipolar[:].next=rxdata[:(nspi-n)].signed() #this passes - but result is 0! (unexpected for me)
bipolar.next=rxdata(nspi,(nspi-n)).signed() #this is the way: use shadow signal !
print(bipolar, 'bipolar=', int(str(bipolar),16))
return instances()
tc = testcase()
tc.run_sim(tend*1e9)
print('Simulated to tend='+str(tend))
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