修改Verilog模式缩进
[英]Modify verilog mode indentation
问题描述
I am trying to have verilog mode indent everything using 2 spaces except decls and always. 
我试图让verilog模式使用除decls之外的所有空格都缩进2个空格。 This is what I added to my .emacs: 这是我添加到.emacs中的内容：
;; `define are not indented
(setq verilog-indent-level-directive 0)
;; always, initial etc not indented
(setq verilog-indent-level-module 0)
;; logic declarations are not indented
(setq verilog-indent-level-declaration 0)
;;2 space indent
(setq verilog-indent-level 2)
;; no indent on list and no indent when on multiple lines
(setq verilog-indent-lists nil)
(setq verilog-cexp-indent 0)
These is the result on a test module 这些是测试模块上的结果
`ifndef MY_MODULE_SV
`define MY_MODULE_SV
module my_module #(
parameter MyPar1 = 16,
parameter MyPar2 = 32
) (
input logic clk,
input logic reset,
//comment indented weirdly
output logic [3:0] result
);
logic [3:0] count;
always @(posedge clk) begin
//comment indented ok
if (reset) begin
count <= 0;
result <= 0;
end
else begin
result <= count;
count <= count+1;
end
end
endmodule; // my_module
`endif
The part that is not correct are the port and parameter list. 不正确的部分是端口和参数列表。 Also the declaration of count gets aligned to the port declarations, which is strange. 而且count声明与port声明对齐，这很奇怪。 I would like this to look like: 我希望这样看起来：
module my_module #(
parameter MyPar1 = 16,
parameter MyPar2 = 32
) (
input logic clk,
input logic reset,
//result signal
output logic [3:0] result
);
I am using emacs 24.3.1 I am not sure how to tweak this using only the variables provided by the verilog mode, any suggestion? 我正在使用emacs 24.3.1，我不确定如何仅使用verilog模式提供的变量来进行调整，有什么建议吗？
1 个解决方案
解决方案1
3 2015-06-30 14:28:43
This doesn't exactly match your requested layout, but what I do is put the #( below the module keyword and split the end paren from the parameter list and the begin paren for the port list onto separate lines. The result is below. All of my indentation is for 3 spaces, but you could tweak that to suit your needs: 这与您要求的布局不完全匹配，但是我要做的是将#(放在module关键字下面，并将参数列表的末尾括号和端口列表的开始括号分隔到单独的行中。结果在下面。全部我的缩进是针对3个空格的，但是您可以根据自己的需要进行调整：
module my_module
#(
parameter MyPar1 = 16,
parameter MyPar2 = 32
)
(
input logic clk,
input logic reset,
//comment indented weirdly
output logic [3:0] result
);
logic [3:0] count;
always @(posedge clk) begin
//comment indented ok
if (reset) begin
count <= 0;
result <= 0;
end
else begin
result <= count;
count <= count+1;
end
end
endmodule; // my_module
The verilog mode related section of my .emacs file is below: 我的.emacs文件的verilog模式相关部分如下：
(custom-set-variables
'(verilog-align-ifelse t)
'(verilog-auto-delete-trailing-whitespace t)
'(verilog-auto-inst-param-value t)
'(verilog-auto-inst-vector nil)
'(verilog-auto-lineup (quote all))
'(verilog-auto-newline nil)
'(verilog-auto-save-policy nil)
'(verilog-auto-template-warn-unused t)
'(verilog-case-indent 3)
'(verilog-cexp-indent 3)
'(verilog-highlight-grouping-keywords t)
'(verilog-highlight-modules t)
'(verilog-indent-level 3)
'(verilog-indent-level-behavioral 3)
'(verilog-indent-level-declaration 3)
'(verilog-indent-level-module 3)
'(verilog-tab-to-comment t))
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