如何使用Verilog模式AUTOINST？

Question

I'm trying to use AUTOINST. my problem is that Module name is different from the it's verilog file name (located under subdir) so the following won't work:

module ExampInout (o,i);
  InstModule instName
  (/*AUTOINST*/);
endmodule

// Local Variables:
// verilog-library-directories:("subdir")
// End:

How can I let verilog mode "know" that InstModule reside under subdir but in file other than InstModule.v?

Answer 1

verilog-library-files is what you're looking for. You can specify a full or relative path to each file in the list.

That said the comment on the question is a good one. Good style is usually to have the module name match the file name. The exception to this is when it's a 'library' file that contains lots of small module definitions.