[英]How to remove I/O port declarations using regexp in verilog mode
I'm trying to instantiate abc_d
module and i don't want all of its ports to be declared as I/O ports in abc
top module. 我正在尝试实例化
abc_d
模块,我不希望它的所有端口都被声明为abc
top模块中的I / O端口。 I want to exclude ex_out_port
to be declared as output
port. 我想排除
ex_out_port
被声明为output
端口。
module abc(/*AUTOARG*/);
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOWIRE*/
abc_d u_abc_d(/*AUTOINST*/);
endmodule
//Localvariables:
//verilog-auto-output-ignore-regexp:("ex_out_port")
//END:
expected code: 预期代码:
module abc (/*AUTOARG*/
/Inputs
input port1;
input port2;
/Outputs
output port3;
output port4;
/*AUTOWIRE*/
wire ex_out_port;
//Instance
abc_d u_abc_d(/*AUTOINST*/
.port1 (port1),
.port2 (port2),
.port3 (port3),
.port4 (port4),
.ex_out_port (ex_out_port)):
endmodule
Related already-answered questions: 相关的已回答问题:
Your verilog-auto-output-ignore-regexp
is slightly off. 你的
verilog-auto-output-ignore-regexp
稍微关闭了。 It works after dropping the parenthesis around "ex_out_port" 在“ex_out_port”周围删除括号后,它可以工作
//verilog-auto-output-ignore-regexp: "ex_out_port"
I was not able to find any code examples gnore-regexp in documentation or FAQ. 我无法在文档或FAQ中找到任何代码示例gnore-regexp。 I did find one example in a forum on the veriloop site (owners of verilog-mode): https://www.veripool.org/boards/15/topics/1635-Verilog-mode-Scope-for-AUTO_LISP-
我确实在veriloop网站(verilog模式的所有者)的论坛中找到了一个例子: https ://www.veripool.org/boards/15/topics/1635-Verilog-mode-Scope-for-AUTO_LISP-
FYI: Unless you are strictly following Verilog-1995 syntax or running obsolete version of verilog-mode, you can consider change: 仅供参考:除非您严格遵循Verilog-1995语法或运行过时版本的verilog-mode,否则您可以考虑更改:
module abc(/*AUTOARG*/);
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOWIRE*/
To an ANSI style header which is supported since Verilog-2001: 到Verilog-2001以来支持的ANSI样式头:
module abc(
/*AUTOINPUT*/
/*AUTOOUTPUT*/
);
/*AUTOWIRE*/
It is functionally and behaviorally the same with fewer lines of generated code. 它在功能和行为上都相同,生成的代码行数较少。
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