使用分配时的verilog_mode autoreginput行为

Question

I wonder if the following case is possible.
I have :

module a(
input [2:0] a_i
);
endmodule

module b ();

 /*AUTOREGINPUTS*/

 a u_a(/*AUTOINST*/)
endmodule

It expands to:

 module b ();

 /*AUTOREGINPUTS*/
 reg [2:0] a_i;
 a u_a(/*AUTOINST*/
       .a_i(a_i))
endmodule

But if I modify adding the line assign a_i = '0; , then it does not expands AUTOREGINPUTS anymore. Is there a way to expand it even if I'm doing an assignment ?

Answer 1

The short answer is because when running verilog-auto to fill in /*AUTOREGINPUT*/ will exclude any signal that is already declared and by adding assign a_i = '0; , you are declaring a_i .

In Verilog, explicit variable declarations are not required and will take on the default nettype if left undeclared under certain circumstances. So, if I had the following:

module x;
  assign myVar = '0;
endmodule

myVar will be implicitly declared to be a net with the default nettype (which by default is wire ). You can read more in the System-Verilog LRM (IEEE1800-2009 Section 6.10). One recommendation to avoid typos generating implicitly declared variables is to change the default nettype with the `default_nettype macro to none (ie `default_nettype none on the top of every file); doing this forces all variables to be explicitly declared or the compiler/synthesizer will throw an error.

verilog-mode mode in emacs is aware of implicit declaration and, as such, will not autogenerate anything declared. Thus, when you add the assign statement, you are declaring a_i and so the autogenerator will not "redefine" a_i .

To avoid this, I can only recommend running the generator before you assign any of the variables to be autogenerated. Im not sure if it handles `default_nettype none correctly, but I would assume not.

Also note, it should be /*AUTOREGINPUT*/ , not /*AUTOREGINPUTS*/ , no 's' at the end.