通过FPGA和1/0引脚连接Parallela板和rPI的堆栈

Question

I want to conect my Pi and Parallella such that the Pi does the GPU side and the Parallella stack this is to be controled by a third Parallella

I think the best way to do this is through an FPGA. Is this possible and a good way to do it?

Also what structure should I use and how should I start to implement it?

I know little VHDL and Verilog and do not want to use paid software.

I am eager to learn and have a lot of time to do it though so no "simple but bad solutions".

I will up load the project on Git when done

Answer 1

The solution depends on the bandwidth and latency requirements. You are right that FPGA provides the largest bandwidth and lowest latency. However, do you really need such good performance? Maybe USB or Ethernet connections are good enough.

For the FPGA solution, consider the secondary pi and parallella as two peripherals for the primary pi, and assign different address spaces for them. The communications among three devices are based on polling initiated by the primary pi. FPGA should pass the signaling on data/address bus to the two peripherals with compatible I/O timing. Peripherals consider the FPGA as a RAM, and should listen to any data/controls with their best effort. FPGA should buffer the data/control signals if peripherals cannot respond in real-time.

Overall, it's a very tough work. I'd like to see the source code if the FPGA solution works.