[英]Verilog D Flip Flop
I'm attempting to write a specific version of the D Flip Flop that uses NOR gates only: 我正在尝试编写仅使用NOR门的D触发器的特定版本:
Following is gate level diagram: 以下是门级图:
The code I'm using in Verilog: 我在Verilog中使用的代码:
module DFlipFlop(D,CLK,Q,QN);
input D, CLK;
output Q, QN;
reg Q, QN, R, S;
always @(negedge CLK) begin
R = ~(~(~(D|S)|R)|CLK);
S = ~(~(D|S)|R|CLK);
Q = ~(R|QN);
QN = ~(S|Q);
end
endmodule
I then uploaded the compiled program to a PLD and it's not flip flopping and I cannot figure out why. 然后,我将编译后的程序上载到PLD,它不是触发器,我也不知道为什么。 I've tried many different things already. 我已经尝试了许多不同的东西。
Note that I have to use the 4 equations in my program for R, S, Q, and QN. 请注意,我必须在程序中将4个方程式用于R,S,Q和QN。
Your problem is the following line: 您的问题是以下行:
always @(negedge CLK) begin
What your circuit is actually creating is a seperate flip flop for each of R
, S
, QN
, and Q
., since you've declared tnis block as being edge-triggered (that's what negedge CLK
means). 电路实际上正在为R
, S
, QN
和Q
分别创建一个单独的触发器,因为您已将tnis块声明为是边沿触发的 (这就是negedge CLK
含义)。 If you want a purely combinational circuit (like what your gate-level diagram shows) you should be using an always @(*)
block instead. 如果要使用纯组合电路(如门级图所示),则应该使用always @(*)
块。
Note that Quartus II has a helpful tool called the RTL Viewer ( Tools->Netlist Viewers->RTL Viewer ) which shows a block-level schematic of your synthesised circuit. 注意,Quartus II有一个有用的工具,称为RTL Viewer ( 工具-> Netlist Viewers-> RTL Viewer ),它显示了合成电路的模块级原理图。 If you look at that, you'll see that you're actually creating four flip-flops (and some logic) with your code, not one. 如果您看一下,您会发现实际上是用代码创建了四个触发器(以及一些逻辑),而不是一个。
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