D 触发器 Verilog 行为实现有编译错误

Question

I have ad flip flop tutorial, and when I try to compile, some errors occur. I've taken this tutorial from technobyte.org , and anything changed, but it doesn't work. D Flip Flop and Test Bench Code is below.

Can you find the problem?

D Flip Flop

module D_Flip_Flop(d,clk,clear,q,qbar);

input d, clk, clear; 
output reg q, qbar; 
always@(posedge clk) 
begin
if(clear== 1)
q <= 0;
qbar <= 1;
else 
q <= d; 
qbar = !d; 
end 
endmodule

Test Bench for D Flip Flop

//test bench for d flip flop
//1. Declare module and ports

module dff_test;
reg D, CLK,reset;
wire Q, QBAR;

//2. Instantiate the module we want to test. We have instantiated the dff_behavior

D_Flip_Flop dut(.q(Q), .qbar(QBAR), .clear(reset), .d(D), .clk(CLK)); // instantiation by port name.

//3. Monitor TB ports
$monitor("simtime = %g, CLK = %b, D = %b,reset = %b, Q = %b, QBAR = %b", $time, CLK, D, reset, Q, QBAR);

//4. apply test vectors
initial begin
  clk=0;
     forever #10 clk = ~clk;  
end 
initial begin 
 reset=1; D <= 0;
 #100; reset=0; D <= 1;
 #100; D <= 0;
 #100; D <= 1;
end 
endmodule

Errors

Answer 1

There are 3 types of syntax errors in your code:

1. You need begin/end around multiple statements in your if/else .
2. The $monitor statement should be inside an initial block.
3. Verilog is case-sensitive. clk was not declared. Change all CLK to clk .

You should report these errors to the person who created that tutorial.

Here is code that compiles cleanly for me. I also added proper indentation to your DFF:

module D_Flip_Flop(d,clk,clear,q,qbar);

input d, clk, clear; 
output reg q, qbar; 
always@(posedge clk) begin
    if(clear== 1) begin
        q <= 0;
        qbar <= 1;
    end else begin 
        q <= d; 
        qbar = !d; 
    end
end
endmodule

module dff_test;
reg D, clk,reset;
wire Q, QBAR;

//2. Instantiate the module we want to test. We have instantiated the dff_behavior

D_Flip_Flop dut(.q(Q), .qbar(QBAR), .clear(reset), .d(D), .clk(clk)); // instantiation by port name.

//3. Monitor TB ports
initial $monitor("simtime = %g, clk = %b, D = %b,reset = %b, Q = %b, QBAR = %b", $time, clk, D, reset, Q, QBAR);

//4. apply test vectors
initial begin
  clk=0;
     forever #10 clk = ~clk;  
end 

initial begin 
 reset=1; D <= 0;
 #100; reset=0; D <= 1;
 #100; D <= 0;
 #100; D <= 1;
end 
endmodule

---

Good coding practice recommends using nonblocking assignments for sequential logic. Change:

qbar = !d; 

to

qbar <= !d;