[英]D Flip Flop Verilog Behavioral Implementation has compile errors
我有广告触发器教程,当我尝试编译时,会出现一些错误。 我从technobyte.org获取了本教程,并进行了任何更改,但它不起作用。 D 触发器和测试台代码如下。
你能找到问题吗?
D 触发器
module D_Flip_Flop(d,clk,clear,q,qbar);
input d, clk, clear;
output reg q, qbar;
always@(posedge clk)
begin
if(clear== 1)
q <= 0;
qbar <= 1;
else
q <= d;
qbar = !d;
end
endmodule
D触发器测试台
//test bench for d flip flop
//1. Declare module and ports
module dff_test;
reg D, CLK,reset;
wire Q, QBAR;
//2. Instantiate the module we want to test. We have instantiated the dff_behavior
D_Flip_Flop dut(.q(Q), .qbar(QBAR), .clear(reset), .d(D), .clk(CLK)); // instantiation by port name.
//3. Monitor TB ports
$monitor("simtime = %g, CLK = %b, D = %b,reset = %b, Q = %b, QBAR = %b", $time, CLK, D, reset, Q, QBAR);
//4. apply test vectors
initial begin
clk=0;
forever #10 clk = ~clk;
end
initial begin
reset=1; D <= 0;
#100; reset=0; D <= 1;
#100; D <= 0;
#100; D <= 1;
end
endmodule
错误
您的代码中有 3 种类型的语法错误:
if/else
中围绕多个语句begin/end
。$monitor
语句应该在初始块内。clk
没有被声明。 将所有CLK
更改为clk
。您应该向创建该教程的人报告这些错误。
这是为我编译干净的代码。 我还为您的 DFF 添加了适当的缩进:
module D_Flip_Flop(d,clk,clear,q,qbar);
input d, clk, clear;
output reg q, qbar;
always@(posedge clk) begin
if(clear== 1) begin
q <= 0;
qbar <= 1;
end else begin
q <= d;
qbar = !d;
end
end
endmodule
module dff_test;
reg D, clk,reset;
wire Q, QBAR;
//2. Instantiate the module we want to test. We have instantiated the dff_behavior
D_Flip_Flop dut(.q(Q), .qbar(QBAR), .clear(reset), .d(D), .clk(clk)); // instantiation by port name.
//3. Monitor TB ports
initial $monitor("simtime = %g, clk = %b, D = %b,reset = %b, Q = %b, QBAR = %b", $time, clk, D, reset, Q, QBAR);
//4. apply test vectors
initial begin
clk=0;
forever #10 clk = ~clk;
end
initial begin
reset=1; D <= 0;
#100; reset=0; D <= 1;
#100; D <= 0;
#100; D <= 1;
end
endmodule
良好的编码实践建议对顺序逻辑使用非阻塞分配。 改变:
qbar = !d;
至
qbar <= !d;
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