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[英]Creating a JK Flip Flop module using an SR Flip Flop Module in Verilog
[英]D Flip flop using JK flip flop and JK flipflop using SR flip flop
Hi试图使用JK触发器以及使用SR触发器的JK-Flip触发器编写结构和测试基准代码。 但是我遇到了一些错误。 请任何人都可以帮助我提前谢谢。 这是我的编码
D2jk的结构
`timescale in/1ps module d2jkflip(j,k,clk,q,qbar); wire D; assign D=(j&~q)|(~k&q); dff DFF0(q,qbar,D,clk); endmodule
D2jk的测试台代码
`timescale in/1ps
module test_d2jkflip(j,k,clk,q,qbar);
input j,k,clk;
wire D;
reg q;
assign qbar=~q;
always @(posedge clk)
if({j,k}==2'b00)
q<=q;
else
if({j,k}==2'b01)
q<=1'b0;
else
if({j,k}==2'b10)
q<=1'b1;
else
if({j,k}==2'b11)
q<=~q;
else
q<=1'bx;
endmodule
得到这样的错误
Error-[PNDIID] Port not defined in IO declaration
d2jk.v, 2
Identifier 'k' is not defined in IO declaration
Source info: : k
Please refer to LRM [1364-2001], section 12.3.3.
Error-[PNDIID] Port not defined in IO declaration
d2jk.v, 2
Identifier 'clk' is not defined in IO declaration
Source info: : clk
Please refer to LRM [1364-2001], section 12.3.3.
Error-[PNDIID] Port not defined in IO declaration
d2jk.v, 2
Identifier 'Qbar' is not defined in IO declaration
Source info: : Qbar
Please refer to LRM [1364-2001], section 12.3.3.
Error-[PNDIID] Port not defined in IO declaration
d2jk.v, 2
Identifier 'Q' is not defined in IO declaration
Source info: : Q
Please refer to LRM [1364-2001], section 12.3.3.
Parsing design file 'test_d2jk.v'
Error-[SE] Syntax error
Following verilog source has syntax error :
"test_d2jk.v", 8: token is '<'
if({j,k}==2'b00) Q< =Q
^
6 errors
jk2sr的结构代码
`timescale 1ns/1ps module jk2sr(j,k,Clk,r,s,Q,Qbar); input j,k; input Clk; input r; input s; input Q; output Qbar; reg Qbar; always@ (posedge(Clk)) begin if(r == 1) Qbar = 0; else if(s == 1) Qbar = 1; else if(Q == 1) if(J == 0 && K == 0) Qbar = Qbar; else if(J == 0 && K == 1) Qbar = 0; else if(J == 1 && K == 0) Qbar = 1; else Qbar = ~Qbar; else Qbar = Qbar; end endmodule
JK2SR的测试基准代码
`timescale 1ns/1ps
module test_jk2sr(s,r,clk,Q,Qbar);
input s,r,clk;
output Q,Qbar;
reg [1:0] sr;
always @(posedge clk)
begin
sr={s,r}
begin
case(sr)
2'd1:Q=1'b0;
2'd2:Q=1'b1;
2'd3:Q=1'b1;
end
endcase
end
else begin
Q=1'b0;
end
Qbar=~Q;
end
endmodule
好吧,看起来这些错误中的大多数来自未定义输入和输出。 您需要指定它,否则会给您错误。 我的建议是选择一种编码样式,使它们的定义更加明显,例如:
module jk2sr (
input wire j,
input wire k,
input wire Clk,
input wire r,
input wire s,
input wire Q,
output reg Qbar
);
// ...
endmodule
我也建议重写
if({j,k}==2'b00)
q<=q;
else
if({j,k}==2'b01)
q<=1'b0;
else
if({j,k}==2'b10)
q<=1'b1;
else
if({j,k}==2'b11)
q<=~q;
else
q<=1'bx;
带有这样的案例声明:
case ({j,k})
2'b00: q <= q;
2'b01: q <= 1'b0;
2'b10: q <= 1'b1;
2'b11: q <= ~q;
default: q <= 1'bx;
endcase
应声明所有IO方向。 亚历克斯发布了一种类型。 这是另一种类型。
module d2jkflip(
j,k,clk,r,s,q,qbar
);
input j,k,clk,r,s,q; //If you don't declare whether these signals are
"wire" or "reg". Their default type is "wire"
output reg qbar;
//output qbar; reg qbar; //This is also legal
// ...
endmodule
通常,在测试台文件中,设计的输入必须为reg
,设计的输出必须为wire
(某些例外,例如设计中的output wire
等)。
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