D Flip flop using JK flip flop and JK flipflop using SR flip flop

Question

Hi was trying to write Both structural and Test bench code for D-flip flop using JK flip flop as well as JK-Flip flop using SR flip flop. but i was getting the some errors. Please anyone could help me out thanks in advance. Here is my Coding

1. structural for D2jk

     `timescale in/1ps module d2jkflip(j,k,clk,q,qbar); wire D; assign D=(j&~q)|(~k&q); dff DFF0(q,qbar,D,clk); endmodule 

Test bench code for D2jk

    `timescale in/1ps

    module test_d2jkflip(j,k,clk,q,qbar);
       input j,k,clk;

       wire  D;

       reg   q;

       assign qbar=~q;

       always @(posedge clk)
         if({j,k}==2'b00) 
           q<=q;
         else
           if({j,k}==2'b01) 
             q<=1'b0;
           else
             if({j,k}==2'b10) 
               q<=1'b1;
             else
               if({j,k}==2'b11) 
                 q<=~q;
               else
                 q<=1'bx;
    endmodule 

getting errors like this

Error-[PNDIID] Port not defined in IO declaration
 d2jk.v, 2
   Identifier 'k' is not defined in IO declaration
  Source info: : k
  Please refer to LRM [1364-2001], section 12.3.3.

Error-[PNDIID] Port not defined in IO declaration

d2jk.v, 2
  Identifier 'clk' is not defined in IO declaration
  Source info: : clk
  Please refer to LRM [1364-2001], section 12.3.3.

Error-[PNDIID] Port not defined in IO declaration

d2jk.v, 2
  Identifier 'Qbar' is not defined in IO declaration
  Source info: : Qbar
  Please refer to LRM [1364-2001], section 12.3.3.

Error-[PNDIID] Port not defined in IO declaration

d2jk.v, 2
  Identifier 'Q' is not defined in IO declaration
  Source info: : Q
  Please refer to LRM [1364-2001], section 12.3.3.

Parsing design file 'test_d2jk.v'
Error-[SE] Syntax error
  Following verilog source has syntax error :
  "test_d2jk.v", 8: token is '<'
  if({j,k}==2'b00) Q< =Q
                     ^
6 errors

2. structural code for jk2sr

    `timescale 1ns/1ps module jk2sr(j,k,Clk,r,s,Q,Qbar); input j,k; input Clk; input r; input s; input Q; output Qbar; reg Qbar; always@ (posedge(Clk)) begin if(r == 1) Qbar = 0; else if(s == 1) Qbar = 1; else if(Q == 1) if(J == 0 && K == 0) Qbar = Qbar; else if(J == 0 && K == 1) Qbar = 0; else if(J == 1 && K == 0) Qbar = 1; else Qbar = ~Qbar; else Qbar = Qbar; end endmodule 

Test bench code for JK2SR

    `timescale 1ns/1ps

    module test_jk2sr(s,r,clk,Q,Qbar);
       input s,r,clk;
       output Q,Qbar;
       reg [1:0] sr;

       always @(posedge clk)
         begin
            sr={s,r}
               begin
                  case(sr)
                    2'd1:Q=1'b0; 
                    2'd2:Q=1'b1;
                    2'd3:Q=1'b1;
                  end       
         endcase  
               end     
    else begin
       Q=1'b0;      
    end   
            Qbar=~Q;
         end 

    endmodule

Answer 1

Well, looks like most of those errors come from not defining inputs and outputs. You need to specify this, otherwise it will give you errors. My suggestion is to pick a coding style that makes defining these more obvious, such as:

module jk2sr (
   input wire j,
   input wire k,
   input wire Clk,
   input wire r,
   input wire s,
   input wire Q,
   output reg Qbar
);

// ...

endmodule

I would also recommend rewriting

     if({j,k}==2'b00) 
       q<=q;
     else
       if({j,k}==2'b01) 
         q<=1'b0;
       else
         if({j,k}==2'b10) 
           q<=1'b1;
         else
           if({j,k}==2'b11) 
             q<=~q;
           else
             q<=1'bx;

with a case statement like so:

case ({j,k})
    2'b00: q <= q;
    2'b01: q <= 1'b0;
    2'b10: q <= 1'b1;
    2'b11: q <= ~q;
    default: q <= 1'bx;
endcase

Answer 2

All IO directions should be declared. Alex posted one type. Here is another type.

module d2jkflip(
  j,k,clk,r,s,q,qbar
);
input j,k,clk,r,s,q;    //If you don't declare whether these signals are
                          "wire" or "reg". Their default type is "wire"
output reg qbar;
//output qbar;    reg qbar;    //This is also legal

// ...

endmodule

And in test bench file, generally speaking, input from your design must be reg , and output to design must be wire (some Exceptions, like output wire in design. etc).