Verilog D Flip Flop

Question

I'm attempting to write a specific version of the D Flip Flop that uses NOR gates only:

Following is gate level diagram:

The code I'm using in Verilog:

module DFlipFlop(D,CLK,Q,QN);
    input D, CLK;
    output Q, QN;
    reg Q, QN, R, S;

always @(negedge CLK) begin
    R = ~(~(~(D|S)|R)|CLK);
    S = ~(~(D|S)|R|CLK); 
    Q = ~(R|QN);
    QN = ~(S|Q);
end

endmodule

I then uploaded the compiled program to a PLD and it's not flip flopping and I cannot figure out why. I've tried many different things already.

Note that I have to use the 4 equations in my program for R, S, Q, and QN.

Answer 1

Your problem is the following line:

always @(negedge CLK) begin

What your circuit is actually creating is a seperate flip flop for each of R , S , QN , and Q ., since you've declared tnis block as being edge-triggered (that's what negedge CLK means). If you want a purely combinational circuit (like what your gate-level diagram shows) you should be using an always @(*) block instead.

Note that Quartus II has a helpful tool called the RTL Viewer ( Tools->Netlist Viewers->RTL Viewer ) which shows a block-level schematic of your synthesised circuit. If you look at that, you'll see that you're actually creating four flip-flops (and some logic) with your code, not one.