[英]Increasing the speed of Xilinx ISim simulation
I have a large ISim design for Spartan-6 using about 6 of the Spartan-6 FPGA IP cores. 我使用约6个Spartan-6 FPGA IP内核为Spartan-6设计了一个大型ISim。 It needs to run for a simulation time of 13 seconds, but at present takes 40 seconds to run a simulation time of 1 ms.
它需要运行13秒的仿真时间,但目前需要40秒才能运行1 ms的仿真时间。 During the 13 seconds it will also write 480000 24 bit std_logic_vectors to a text file.
在13秒钟内,它还会将480000个24位std_logic_vectors写入文本文件。
This equates to running time of 144 hours to run the entire simulation (almost a week!). 这相当于需要144小时的运行时间来运行整个模拟(几乎一周!)。
Is there a way, for example, of increasing the step size or turning off the settings for waveform plotting etc, or any other settings I can use to increase the simulation speed? 有没有办法增加步长或关闭波形图等设置,或者可以使用其他设置来提高仿真速度?
So far I have tried not plotting the waveform, but it doesn't seem to actually increase the speed. 到目前为止,我还没有尝试绘制波形图,但是它似乎并没有真正提高速度。
Thanks very much 非常感谢
Yes adding signals to the waveform slowes every simulator down... but running such long simulations always create GiB of data and take hours or days. 是的,向波形中添加信号会减慢每个模拟器的速度……但是运行如此长时间的模拟总是会产生GiB数据,并且要花费数小时或数天。
You could check your code and: 您可以检查代码并:
But in general there is only one solution: use another simulator. 但通常只有一种解决方案:使用另一种模拟器。 Especially one with optimization.
特别是具有优化的功能。 (Can be disabled or restricted in free editions) Eg:
(可以在免费版本中禁用或限制),例如:
PS 40 sec for 1 ms (25 us per second) is very fast. PS 40秒(1毫秒)(每秒25 us)非常快。 My integration simulations usually calculate 20 ns per second.
我的集成仿真通常每秒计算20 ns。 So you are 1000x faster)
所以您快了1000倍)
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