[英]Verilog error : Unable to bind parameter in module
I'm new to Verilog, I'd really appreciate it if someone could help me figure this error out: 我是Verilog的新手,如果有人可以帮助我解决此错误,我将非常感谢:
I'm trying to write a test bench PU_tb , which is instantiating this module: 我正在尝试编写一个测试平台PU_tb ,以实例化此模块:
PU_conv #(
.image_width ( image_width ),
.image_height ( image_height ),
.kernel_width ( kernel_width ),
.kernel_height ( kernel_height )
) convolution (
.ACLK ( ACLK ), //input
.image ( image ), //input
.kernel ( kernel ), //input
.result ( result ) //output
);
The module PU_conv looks like this: 模块PU_conv如下所示:
module PU_conv
#( //Parameters
parameter integer image_width = 10,
parameter integer image_height = 4,
parameter integer kernel_width = 2,
parameter integer kernel_height = 2
)( //PORTS
input wire ACLK,
input wire [0:image_width][image_height:0] image,
input wire [0:kernel_width][kernel_height:0] kernel,
output reg [0:image_width][image_height:0] result
);
I'm getting this error: 我收到此错误:
error: Unable to bind parameter 'image_height' in 'PU_tb'
错误:无法在“ PU_tb”中绑定参数“ image_height”
error: Unable to bind parameter 'image_width' in 'PU_tb'错误:无法在“ PU_tb”中绑定参数“ image_width”
error: Unable to bind parameter 'kernel_height' in 'PU_tb'错误:无法在“ PU_tb”中绑定参数“ kernel_height”
error: Unable to bind parameter 'kernel_width' in 'PU_tb'错误:无法在“ PU_tb”中绑定参数“ kernel_width”
The kernel and image widths and heights are declared as follows: 内核和图像的宽度和高度声明如下:
reg[5:0] param_kw;
reg[5:0] param_kh;
reg[5:0] param_iw;
reg[5:0] param_ih; ....
integer kernel_width, kernel_height, image_width, image_height;
always @(param_kw)
kernel_width = param_kw;
always @(param_kh)
kernel_height = param_kh;
always @(param_iw)
image_width = param_iw;
always @(param_ih)
image_height = param_ih;
What am I doing wrong? 我究竟做错了什么?
The following code works fine. 以下代码可以正常工作。 Make sure you have declared parameters correctly in top/tb module.
确保在top / tb模块中正确声明了参数。
module PU_conv
#( //Parameters
parameter integer image_width = 10,
parameter integer image_height = 4,
parameter integer kernel_width = 2,
parameter integer kernel_height = 2
) ( //PORTS
input wire ACLK,
input wire [0:image_width][image_height:0] image,
input wire [0:kernel_width][kernel_height:0] kernel,
output reg [0:image_width][image_height:0] result
);
initial
begin
$display("image_width = %0d image_height = %0d",image_width,image_height);
$display("kernel_width = %0d kernel_height = %0d",kernel_width,kernel_height);
end
endmodule
module top();
parameter integer image_width = 8;
parameter integer image_height = 7;
parameter integer kernel_width = 6;
parameter integer kernel_height = 5;
wire ACLK;
wire [0:image_width][image_height:0] image;
wire [0:kernel_width][kernel_height:0] kernel;
reg [0:image_width][image_height:0] result;
PU_conv #(
.image_width ( image_width ),
.image_height ( image_height ),
.kernel_width ( kernel_width ),
.kernel_height ( kernel_height )
) convolution (
.ACLK ( ACLK ), //input
.image ( image ), //input
.kernel ( kernel ), //input
.result ( result ) //output
);
endmodule
Multi dimensional arrays as inputs are supported in SystemVerilog only. 仅在SystemVerilog中支持将多维数组作为输入。 Following is the output display:
以下是输出显示:
// Overridden parameters
image_width = 8 image_height = 7
kernel_width = 6 kernel_height = 5
Similar question is posted in Verilog Parameter over ridding . 类似的问题发布在Verilog Parameter over riding上 。
声明:本站的技术帖子网页,遵循CC BY-SA 4.0协议,如果您需要转载,请注明本站网址或者原文地址。任何问题请咨询:yoyou2525@163.com.