生成块的执行

Question

1. When is "GENERATE BLOCK" executed in a Verilog module ?
2. Will the code inside Generate Block execute sequentially ?

Answer 1

Generate block cannot be executed like always or initial blocks, it is evaluated during elaboration stage. Generate is commonly used to instantiate multiple instance of same module or logic, for example:

module and_mod (input bit a, input bit b, output out);
  assign out = a & b;
endmodule


module test #( 
   parameter NUM_INSTANCES = 3 
) (
   input bit [NUM_INSTANCES - 1 : 0] a, 
   input bit [NUM_INSTANCES - 1 : 0] b, 
   output bit [NUM_INSTANCES - 1 : 0] a_and_b, 
   output bit [NUM_INSTANCES - 1 : 0] a_or_b,
   output bit [NUM_INSTANCES - 1 : 0] a_xor_b
);


   genvar i;
   generate 
      for( i = 0; i < NUM_INSTANCES; i++ )
      begin
        //module instance
        and_mod and_inst (.a(a[i]),.b(b[i]), .out(a_and_b[i]));
        //contionous assignement                         
        assign a_xor_b[i] = a[i] ^ b[i]; 

        //always block
        always @(*)
        begin
          a_or_b[i] = a[i] | b[i];
        end
      end
    endgenerate
endmodule

This generate block will evaluate to NUM_INSTANCES copies of code inside generate block. As you can see you can have module instantiation, assignments, always/initial blocks inside generate block. Pay attention to the fact that and_mod has only 1-bit wide ports so we need 3 instances of it to calculate and of 3-bit registers, but thanks to generate block you don't have to write 3 instances in your code.

Execution of code inside generate block depends on code itself, assignments will execute concurrently, code inside always block will execute sequentially, same as without generate block.

You can test it here .

Answer 2

generate block is not for execution. It is just that if you want to have multiple repetitive blocks in a module, then you can use generate block.

Generate constructs are used to either conditionally or multiply instantiate generate blocks into a model.

A generate block is a collection of one or more module items. A generate block may not contain port declarations, specify blocks, or specparam declarations. Parameters declared in generate blocks shall be treated as localparams. All other module items, including other generate constructs, are allowed in a generate block.

Generate constructs provide the ability for parameter values to affect the structure of the design. They also allow for modules with repetitive structure to be described more concisely, and they make recursive module instantiation possible.

Generate schemes are evaluated during elaboration of the design. They do not execute at simulation time. They are evaluated at elaboration time, and the result is determined before simulation begins.

Refer to Topic 27, in SV1800-2012 LRM for more details.