Verilog中的计算逻辑生成块

Question

am trying to instantiate a simple module in a generate block with different hierarchical clocks. But facing this issue:

Error-[SE] Syntax error Following verilog source has syntax error : "testbench/tb/uflex_ilk_comp_ext_s10_top_cr3.sv", 242: token is '='
genvar j=i/4; ^

`define CLK uflex_ilk_comp_ext_s10_top.dut.soft_pcs_pam4.pam4_phy_inst[j].pam4_phy.nphy.g_xcvr_native_insts[k].ct3_xcvr_native_inst.inst_ct3_xcvr_channel.inst_ct3_hssi_xcvr.ct3_hssi_xcvr_encrypted_inst.ct1_hssirtl_c3xcvr_inst.u_serdes.corif_serial_clk_tx


genvar i;
generate
  for (i=0; i<NUM_LANES; i++) begin:delay_bmod_inst
genvar j=i/4;  --> Using j and k in CLK define
genvar k=i%4;
    txrx_delay_bmod #(.LANE_NUM(i), .MAX_LANE_DELAY(107), .GROUP_DELAY_RANGE(17)) txrx_delay_bmod_1 (
        .clk(`CLK),
        .i_tx_data(tx_serial_data[i]),
        .o_tx_data(tx_serial_data_dly[i])
    );
  end
endgenerate

Answer 1

You are not allowed to assign to a genvar . This is illegal:

genvar j=i/4;

Hence your error message.

Answer 2

If you are using SystemVerilog, you can write as

for (genvar i=0; i<NUM_LANES; i++) begin:delay_bmod_inst
  localparam j=i/4;  //--> Using j and k in CLK define
  localparam k=i%4;
  txrx_delay_bmod #(.LANE_NUM(i), .MAX_LANE_DELAY(107), .GROUP_DELAY_RANGE(17)) 
         txrx_delay_bmod_1 (
        .clk(`CLK),
        .i_tx_data(tx_serial_data[i]),
        .o_tx_data(tx_serial_data_dly[i])
    );
  end