在verilog中在generate块下修改实例化名称

Question

Some body suggest me how to get the instantiation name without "." like "genblk1.name" if i use generate for loop for creating more module instantiations.

I want instantiation names like addr_1,addr_2 (addr my module name)

Answer 1

You'll always get a "." when you instantiate modules inside generate blocks. This is because every generate block creates a new level of hierarchy. The first string is the name of the generate block, while the second is the name of the instance. The only thing you can do is control the name of the generate block:

module some_module;
endmodule // some_module


module top;
  parameter a = 1;
  if (a) begin : if_gen_block
    some_module inst();
  end

  genvar i;
  for (i = 0; i < 5; i++) begin : loop_gen_block
    some_module inst();
  end
endmodule // top

The if generate block will create "if_gen_block.inst", whereas the for gen block will create 'loop_gen_block[0].inst', 'loop_gen_block[1].inst', etc. This behavior is specified in the SystemVerilog LRM.