跨时钟域，用于罕见地更改数据

Question

I need to connect a configuration module (running at slower clock) to a worker which runs at higher speed. Standard answer seems to be a FIFO but I thought I come up with a simpler solution which consumes less resources - with drawback of having much higher latency. Benefit for me is that I don't need to regenerate FIFO IP for each possible size of data. In RTL simulation it seems to work (I run into troubles using post-synthesis one unrelated to question).

Am I missing something or is the following code correct:

module fifo_int#( // This is bad name. I haven't come up with better yet
    parameter type DATA = logic [31:0]
    )(
    input  logic rst,
    input  logic clk_in,
    input  DATA  din,
    input  logic clk_out,
    output DATA  dout
    );
    DATA dreg;

    enum logic [1:0] {
        IN,
        STABLE,
        WAIT_OUT
    } in_state;
    enum logic [1:0] {
        WAIT_IN,
        WRITE,
        INV
    } out_state;
    logic in_output[3], out_output[3];
    initial begin
        in_state <= IN;
        out_state <= WAIT_IN;
        for (int i = 0; i < 3; i++) begin
            in_output[i] <= 0;
            out_output[i] <= 0;
        end
    end
    always @(posedge clk_in)
    begin
        case (in_state)
        IN: begin
            dreg <= din;
            in_state <= STABLE;
        end
        STABLE: begin
            in_state <= WAIT_OUT;
            in_output[0] <= ~in_output[0];
        end
        WAIT_OUT: begin
            in_state <= (in_output[0] == out_output[2]) ? IN : WAIT_OUT;
        end
        endcase
        out_output[1] <= out_output[0];
        out_output[2] <= out_output[1];
    end
    always @(posedge clk_out)
    begin
        case (out_state)
        WAIT_IN: begin
            out_state <= (in_output[2] == out_output[0]) ? WAIT_IN : WRITE;
        end
        WRITE: begin
            dout <= dreg;
            out_state <= INV;
        end
        INV: begin
            out_output[0] <= ~out_output[0];
            out_state <= WAIT_IN;
        end
        endcase
        in_output[1] <= in_output[0];
        in_output[2] <= in_output[1];
    end
endmodule

Answer 1

If your clocks are asynchronous, you're going to need synchronization.

For synchronous clocks, since your slow side is the one producing the data, you don't need any buffering. Data is anyway held stable for multiple (fast) clock cycles, so you don't really need any logic between the domains.