[英]python myhdl package how to generate verilog initial block
From the code mostly from the sample of myhdl: 从大部分来自myhdl示例的代码中:
from myhdl import Signal, intbv, delay, always, now, Simulation, toVerilog
__debug = True
def ClkDriver(clk):
halfPeriod = delay(10)
@always(halfPeriod)
def driveClk():
clk.next = not clk
return driveClk
def HelloWorld(clk, outs):
counts = intbv(3)[32:]
@always(clk.posedge)
def sayHello():
outs.next = not outs
if counts >= 3 - 1:
counts.next = 0
else:
counts.next = counts + 1
if __debug__:
print "%s Hello World! outs %s %s" % (
now(), str(outs), str(outs.next))
return sayHello
clk = Signal(bool(0))
outs = Signal(intbv(0)[1:])
clkdriver_inst = ClkDriver(clk)
hello_inst = toVerilog(HelloWorld, clk, outs)
sim = Simulation(clkdriver_inst, hello_inst)
sim.run(150)
I expect it to generate a verilog program that contains an initial
block, like something: 我希望它生成一个包含
initial
块的verilog程序,例如:
module HelloWorld(...)
reg [31:0] counts;
initial begin
counts = 32'h3
end
always @(...
How can you get the initial
block generated? 如何获得
initial
块?
Note that on the google cache for old.myhdl.org/doku.php/dev:initial_values it links to example https://bitbucket.org/cfelton/examples/src/tip/ramrom/ . 请注意,在old.myhdl.org/doku.php/dev:initial_values的Google缓存上,它链接到示例https://bitbucket.org/cfelton/examples/src/tip/ramrom/ 。 So it looks the feature should be supported.
因此,看起来应该支持该功能。 However the rom sample generates static case statements.
但是,rom示例会生成静态case语句。 That's not what I'm looking for.
那不是我要找的东西。
Three steps to resolve it: 解决此问题的三个步骤:
87784ad
which added the feature under issue #105
or #150
. 87784ad
的版本的87784ad
,该哈希值87784ad
在问题#105
或#150
下添加了功能。 As an example for virtualenv, run a git clone, followed by pip install -e <path-to-myhdl-dir>
. pip install -e <path-to-myhdl-dir>
。 toVerilog.initial_values=True
before calling toVerilog
. toVerilog
之前将toVerilog.initial_values=True
设置toVerilog.initial_values=True
。 Code snippet follows. 代码段如下。
def HelloWorld(clk, outs):
counts = [Signal(intbv(3)[32:])]
@always(clk.posedge)
def sayHello():
outs.next = not outs
if counts[0] >= 3 - 1:
counts[0].next = 0
else:
counts[0].next = counts[0] + 1
if __debug__:
print "%s Hello World! outs %s %s %d" % (
now(), str(outs), str(outs.next), counts[0])
return sayHello
clk = Signal(bool(0))
outs = Signal(intbv(0)[1:])
clkdriver_inst = ClkDriver(clk)
toVerilog.initial_values=True
hello_inst = toVerilog(HelloWorld, clk, outs)
sim = Simulation(clkdriver_inst, hello_inst)
sim.run(150)
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