[英]Dynamic Instantiation: How to dynamically wire interfaces in myHDL
I'm trying to make a python library for dynamically making a UART interface between a PC and FPGA using pySerial using myHDL 1.0dev 我正在尝试制作一个python库,以便使用pySerial和myHDL 1.0dev在PC和FPGA之间动态创建UART接口
It takes names for datatypes and their properties, and instantiates a RAM block, as well as allow access to read/write commands on the PC. 它获取数据类型及其属性的名称,并实例化RAM块,并允许访问PC上的读/写命令。 However, I'm running into problems dynamically wiring the RAMs. 但是,我在动态连接RAM时遇到了问题。
For a minimal working example, I have these two classes. 作为一个最小的工作示例,我有这两个类。
class RamBus(object):
def __init__(self):
self.clk = Signal(bool(0))
class UartBus(object):
def __init__(self):
self.interfaces = dict()
def add(self, name, bus):
self.interfaces[name] = bus
setattr(self,name,bus)
UartBus is for holding many RamBuses. UartBus用于容纳许多RamBuse。 Now I'll try to dynamically connect them with the arbiter
block. 现在,我将尝试将它们与arbiter
模块动态连接。
@block
def arbiter(clk,uartbus):
modules = []
for key in uartbus.interfaces:
print key
@block
def electrician(rambus=uartbus.interfaces[key]):
@always_comb
def wiring():
rambus.clk.next = clk
return wiring
f = electrician
modules.append(electrician())
return modules
If I convert it with this code, I get an incorrect conversion 如果使用此代码进行转换,则会得到错误的转换
uartbus = UartBus()
uartbus.add('power',RamBus())
uartbus.add('freq',RamBus())
#attempt conversion
clk = Signal(bool(0))
arbiter(clk,uartbus).convert()
Here's the incorrect verilog. 这是错误的Verilog。
`timescale 1ns/10ps
module arbiter (
clk
);
input clk;
wire electrician_0_rambus_clk;
wire electrician_0_rambus_clk;
assign electrician_0_rambus_clk = clk;
assign electrician_0_rambus_clk = clk;
endmodule
And both wires have the same name! 而且这两根线的名称相同! Using dictionaries in side the @always_comb doesn't work because dictionaries aren't supported by any version of myHDL so far for conversion. 在@always_comb旁边使用字典不起作用,因为到目前为止,任何版本的myHDL都不支持字典进行转换。 How do I correctly implement dynamic wiring? 如何正确实现动态接线?
So I found out the answer, while I was writing this, and since I think its a useful trick to know I decided to post the question anyways. 因此,我在写这篇文章的时候就找到了答案,因为我认为这是一个有用的窍门,所以我决定还是发布问题。
@block
def arbiter(clk,uartbus):
modules = []
for key in uartbus.interfaces:
#note that there is no @block here!
def electrician(rambus=uartbus.interfaces[key]):
@always_comb
def wiring():
rambus.clk.next = clk
return wiring
#here we can redefine the name that electrician
#has so that myHDL converts it with that name.
electrician.func_name = key
#then we apply the block decorator
electrician = block(electrician)
modules.append(electrician())
print key
return modules
And here is the correct verilog. 这是正确的Verilog。
// File: arbiter.v
// Generated by MyHDL 1.0dev
// Date: Tue Jun 28 14:03:01 2016
`timescale 1ns/10ps
module arbiter (
clk
);
input clk;
wire freq_0_rambus_clk;
wire power_0_rambus_clk;
assign freq_0_rambus_clk = clk;
assign power_0_rambus_clk = clk;
endmodule
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