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如何在凿子2.0中制作黑匣子?

[英]How can I make a blackbox in chisel 2.0?

I wrote this code: The verilog code is just the gate: 我写了这段代码: verilog代码只是门:

import Chisel._

class BB_tb extends Bundle {

    val a = Bits(INPUT,  1)
    val b = Bits(INPUT,  1)
    val c = Bits(OUTPUT, 1)
  }



class BlackBox_tb extends BlackBox { 
  val io = new BB_tb() 
}

But I am getting these errors when trying to run it: I don't know what it means 但是我在尝试运行它时遇到这些错误:我不知道这意味着什么

run BlackBox_tb --backend c --targetDir ../emulator --compile [info] Compiling 1 Scala source to /home/essam/intensivate-developer_resources-a25f02d3592d/chisel-tutorial/problems/target/scala-2.11/classes... [info] Running TutorialProblems.TutorialProblems BlackBox_tb --backend c --targetDir ../emulator --compile [error] (run-main-0) scala.MatchError: BlackBox_tb (of class java.lang.String) scala.MatchError: BlackBox_tb (of class java.lang.String) at TutorialProblems.TutorialProblems$.main(problems.scala:9) at TutorialProblems.TutorialProblems.main(problems.scala) at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) at java.lang.reflect.Method.invoke(Method.java:498) [trace] Stack trace suppressed: run last compile:run for the full output. 运行BlackBox_tb-后端c --targetDir ../emulator --compile [info]将1个Scala源代码编译到/home/essam/intensivate-developer_resources-a25f02d3592d/chisel-tutorial/problems/target/scala-2.11/classes。 。[info]正在运行TutorialProblems.TutorialProblems BlackBox_tb-后端c --targetDir ../emulator --compile [错误](run-main-0)scala.MatchError:BlackBox_tb(类java.lang.String)scala.MatchError :位于TutorialProblems.TutorialProblems $ .main(problems.scala:9)处的BlackBox_tb(属于java.lang.String类),位于sun.reflect.NativeMethodAccessorImpl.invoke0(本地方法)处,位于sun.reflect.NativeMethodAccessorImpl.invoke0(本地方法)处.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62)位于java.lang.reflect.Method.invoke(Method.java:498)上的sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)[trace]堆栈跟踪抑制:运行最后一次compile:run以获取完整输出。 java.lang.RuntimeException: Nonzero exit code: 1 at scala.sys.package$.error(package.scala:27) [trace] Stack trace suppressed: run last compile:run for the full output. java.lang.RuntimeException:非零退出代码:scala.sys.package $ .error(package.scala:27)处为1 [trace]禁止堆栈跟踪:运行最后一次compile:run以获取完整输出。 [error] (compile:run) Nonzero exit code: 1 [error] Total time: 18 s, completed Sep 9, 2017 2:30:45 PM [错误](编译:运行)非零退出代码:1 [错误]总时间:18秒,已完成2017年9月9日2:30:45 PM

How important is it that this be done in Chisel2? 在Chisel2中执行此操作有多重要? Chisel3 is now the standard release, and a lot of these things are easier and better supported in it. Chisel3现在是标准版本,并且其中许多功能都更容易获得更好的支持。 In chisel3 the following works for me. 在chisel3中,以下对我有用。

// See LICENSE for license details.

package essan

import chisel3._
import chisel3.iotesters.PeekPokeTester
import chisel3.util.HasBlackBoxResource

class BBAnd extends BlackBox with HasBlackBoxResource {
  val io = IO(new Bundle {
    val a = Input(Bool())
    val b=  Input(Bool())
    val result = Output(Bool())
  })
  val blackBoxFloatVerilog = "/essan/BBAnd.v"
  setResource(blackBoxFloatVerilog)
}

class BBWrapper extends Module {
  val io = IO(new Bundle {
    val a = Input(Bool())
    val b=  Input(Bool())
    val result = Output(Bool())
  })

  val tb = Module(new BBAnd)
  tb.io.a := io.a
  tb.io.b := io.b
  io.result := tb.io.result
}

class BlackBox_tbTests(c: BBWrapper) extends PeekPokeTester(c) {
  // FILL THIS IN HERE
  poke(c.io.a, 1)
  poke(c.io.b, 1)
  // FILL THIS IN HERE
  step(1)
  expect(c.io.result, 1)
}

object BlackBox_tbTests {
  def main(args: Array[String]): Unit = {
    iotesters.Driver(() => new BBWrapper, "verilator") { c =>
      new BlackBox_tbTests(c)
    }
  }
}

I used the following as the underlying verilog implementation 我将以下内容用作基础的Verilog实现

module BBAnd(
    input  [63:0] a,
    input  [63:0] b,
    output reg [63:0] result
);
  always @* begin
  result = a & b;
  end
endmodule

The only real trick was figuring out where to put the verilog implementation. 唯一真正的窍门是弄清楚将verilog实现放在哪里。 The file tree looks like. 文件树看起来像。

src
src/main
src/main/resources
src/main/resources/essan
src/main/resources/essan/BBAnd.v
src/main/scala
src/main/scala/essan
src/main/scala/essan/BlackBoxAnd.scala

I ran the test from the command line with 我从命令行运行了测试

sbt 'runMain essan.BlackBox_tbTests'

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