SystemVerilog字符串化（`“）运算符和换行符

Question

I'm using the SystemVerilog stringify operator, `" , in a macro, as below. The case is deliberately contrived to show the bug:

module my_test();
    `define print(x) $fwrite(log_file, `"x`")
    `define println(x) $fwrite(log_file, `"x\n`")
    integer log_file;

    initial begin
        log_file = $fopen("result.txt", "w");
        `print(A);
        `print(B);
        `println(C);
        `println(D);
        `print(E);
        `print(F);
    end
endmodule

This gives the output (no trailing newline):

ABC
`D
`EF

Why are there ` s in the output, but only from the println ?
Is this documented behaviour in the spec, or a bug in my simulator (Aldec Active-HDL)?

Answer 1

This is a bug in your tool. However, the second `" is not needed and gives you the results you are looking for.