[英]SystemVerilog: implies operator vs. |->
Recently the question came up what the difference is between the usual implication operator ( |->
) and the implies
operator in SystemVerilog. 最近出现的问题是通常的蕴涵算子( |->
)和SystemVerilog中的implies
运算符之间的区别。 Unfortunately I couldn't find a clear answer yet. 不幸的是我还没找到一个明确的答案。 However, I collected the following information: 但是,我收集了以下信息:
From SystemVerilog LRM 1800-2012 : 从SystemVerilog LRM 1800-2012 :
§ 16.12.7 Implies and iff properties : §16.12.7 隐含和iff属性 :
property_expr1 implies property_expr2
A property of this form evaluates to true if, and only if, either property_expr1 evaluates to false or property_expr2 evaluates to true. 当且仅当property_expr1的计算结果为false或property_expr2的计算结果为true时,此表单的属性才会计算为true。
§ F.3.4.3.2 Derived Boolean operators : §F.3.4.3.2 派生的布尔运算符 :
p1 implies p2 ≡ (not p1 or p2)
§ F.3.4.3.4 Derived conditional operators : §F.3.4.3.4 派生的条件运算符 :
(if(b) P) ≡ (b |-> P)
However, the LRM does not really point out what the actual difference is. 但是,LRM并没有真正指出实际差异是什么。 I assume that they differ in the evaluation in case of a false antecedent (success vs. vacuous success), but I could not find any source or evidence for this assumption. 我假设他们在错误的前因(成功与空洞的成功)的情况下评价不同,但我找不到任何这种假设的来源或证据。 Moreover, I know that the implies
operator is very common in combination with formal verification tools like OneSpin. 此外,我知道, implies
运算符与OneSpin等形式验证工具相结合非常常见。
Could anyone help me out? 任何人都可以帮我吗?
PS: It seems there is an answer to this question in the following book: SystemVerilog Assertions Handbook, 3rd Edition . PS:在下面的书中似乎有这个问题的答案: SystemVerilog Assertions Handbook,3rd Edition 。 But $155 is a bit too much for me just for getting the answer to this question :) 但是155美元对我来说有点太多了,只是为了得到这个问题的答案:)
I think there is even a more significant difference. 我认为甚至有更显着的差异。 Assume that we have the following example: 假设我们有以下示例:
property p1;
@ (posedge clk)
a ##1 b |-> c;
endproperty
property p2;
@ (posedge clk)
a ##1 b implies c;
endproperty
assert property (p1);
assert property (p2);
Both implication operators simply have different proving behavior. 两个蕴涵算子都具有不同的证明行为。 Property p1
will be triggered through a match of a ##1 b
and will look for a matching c
during the same clock tick as b
. 属性p1
将通过a ##1 b
的匹配触发,并将在与b
相同的时钟周期内查找匹配的c
。 However, property p2
is triggered by a ##1 b
and will check for a match of c
during the clock cycle of a
. 然而,属性p2
通过触发a ##1 b
,将检查匹配的c
的时钟周期期间a
。 This means the properties would pass for the following scenarios: 这意味着属性将通过以下方案:
Property p1 passes and p2 fails: 属性p1通过,p2失败: Property p2 passes and p1 fails: 属性p2通过,p1失败:
A hint for this behavior can be found in the SystemVerilog LRM. 可以在SystemVerilog LRM中找到有关此行为的提示。 The defined substitutions are: 定义的替换是:
(if(b) P) = (b |-> P)
p1 implies p2 = (not p1 or p2)
So all in all, if one uses the implies operator it becomes easier to define multi-cycle operations since antecedent and consequence have the same starting point for the evaluation. 总而言之,如果使用含义运算符,则定义多周期运算变得更容易,因为先行和后果具有相同的评估起点。
I tried it out and apparently the |->
is not allowed for properties (only for sequences and boolean expressions). 我试了一下,显然不允许|->
属性(仅用于序列和布尔表达式)。 Here's what I tried: 这是我试过的:
property a_and_b;
@(posedge clk)
a && b;
endproperty
property a_and_c;
@(posedge clk)
a && c;
endproperty
First form using |->
doesn't compile: 使用|->
第一个表单不能编译:
// this doesn't compile
assert property(a_and_b |-> a_and_c);
Second form using implies
does compile: 第二种形式使用implies
会编译:
// this does compile
assert property(a_and_b implies a_and_c);
Semantic-wise, it's as it is for the |->
operator. 语义方面,它与|->
运算符一样。 When a_and_b
fails, the assertion vacuously passes. 当a_and_b
失败时,断言a_and_b
通过。 If a_and_b
succeeds but b_and_c
doesn't, then a fail is issued. 如果a_and_b
成功但b_and_c
没有,则发出失败。
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