有模块时为什么要在verilog中使用函数

Question

Part 1 :

I was always told to use functions in Verilog to avoid code duplication. But can't I do that with a module? If my understanding is correct, all functions can be re-written as modules in Verilog except that modules cannot be instantiated from the inside of an always block. Except, in this case, I can always stick with modules. Am I correct?

Part 2 :

If I am correct, why can't the Verilog compiler be written in such a way that the modules get the treatment of a function? I mean, why can't the compiler allow the programmer to instantiate a module inside n block and stop supporting functions?

Answer 1

1. module != function. Their usage in verilog is completely different.

Functions are actually extended expressions and it is used in expressions. It can be used in rhs expression of the 'assign' statement or in expressions inside any procedural block.

• Functions cannot consume time.

• Functions must return a value.

Modules are used to express hardware hierarchy and contain concurrent procedural blocks (which might contain functions).

• Modules may consume time.

• Modules cannot return value. (output ports are not return values)

Potentially you can create a function which replaces internals of a single always block and write an equivalent module with an always block which returns function. But this is it.

2. You are not correct :). Verilog compiler cannot be written in such a way, because there is a verilog standard which every verilog compiler must follow. Otherwise it will not be verilog.